| Message ID | 20241106081826.1211088-4-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add audio support for the Renesas RZ/G3S SoC | expand |
On Wed, Nov 06, 2024 at 10:17:58AM +0200, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > There are some differences b/w 5L35023 and 5P35023 Versa3 clock > generator variants but the same driver could be used with minimal > adjustments. The identified differences are PLL2 Fvco, the clock sel > bit for SE2 clock and different default values for some registers. This is one of the best commit messages I saw for such simple binding change. Much appreciated, thank you. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > Documentation/devicetree/bindings/clock/renesas,5p35023.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 42b6f80613f3..162d38035188 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -31,6 +31,7 @@ description: | properties: compatible: enum: + - renesas,5l35023 - renesas,5p35023 reg: