From patchwork Mon Nov 11 00:47:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13870084 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6C061AD58; Mon, 11 Nov 2024 00:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731286057; cv=none; b=WXbI46bubxNiHyQys3tOT5KnL6GZUuJ3+ERWomgSCC0Wdg+TBtEoXFLIG/P+PjTxoz6qMJUwl+ssNbp2HlvrtFnqtrYbeLiByBM2RBCYWX3EyYqIZsGyvCMgkR8DQEyi2wPK6PP4mgNd7EKX4UEpeFGETVYbOLmWJ617eZgpcX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731286057; c=relaxed/simple; bh=m4/4iJgSTVYMuWJ0b8WwgpT15Wijn6PVhTv10/RvfL0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tg/ySgvbIUIrzAxDLr7bG0OPEClndYtX5bxRwxFax5RTi5n9ksONukJzH2b3bJIAV7aZVmG4loT9zilHoWkkPl0t62Jn6ZdaoSayecUdZcXndGom6S2eZ7wrcdaoar0oNLi+cyL24oqeynMg9NKJ7zY3lQXUemuwpyI4ld1xqRw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A0A621480; Sun, 10 Nov 2024 16:48:04 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B79663F66E; Sun, 10 Nov 2024 16:47:32 -0800 (PST) From: Andre Przywara To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Philipp Zabel , Icenowy Zheng , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] clk: sunxi-ng: mp: Add SUNXI_CCU_P_DATA_WITH_MUX_GATE wrapper Date: Mon, 11 Nov 2024 00:47:16 +0000 Message-ID: <20241111004722.10130-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241111004722.10130-1-andre.przywara@arm.com> References: <20241111004722.10130-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PRCM CCU in the A523 SoC contains some clocks that only feature a P (shift) factor, but no M divider. Treat this as a special case of an MP clock: by forcing the M mask to be 0 bits wide, this always result in the M divider value to be 1. Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu_mp.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h index 6e50f3728fb5f..e235fdfde2d36 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.h +++ b/drivers/clk/sunxi-ng/ccu_mp.h @@ -71,6 +71,24 @@ struct ccu_mp { } \ } +#define SUNXI_CCU_P_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _pshift, _pwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_mp _struct = { \ + .enable = _gate, \ + .m = _SUNXI_CCU_DIV(0, 0), \ + .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \ + .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ + _parents, \ + &ccu_mp_ops,\ + _flags), \ + } \ + } + #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ _mshift, _mwidth, \ _pshift, _pwidth, \