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b=P6F8pc26tjlUULbUn5a7PH5++tP1BxlmBq6e1xiIWlkFRKa38vEYKolIwsxPfJKqq8g+j93yaS1EwDz/rG787iMO0lzZhhrkNM51PjH3Tw+Oli6TPGxTra3WZN0cL0veIeS6VVkkoQCxLPtdWCgIGU8x6Qx3paAUeCwezb1LyW3q7R63jhnQCcE5KBvjOlKTtSOwZvIhioAJGOj7yQ30wFp2qIxe2fHl4csfDVhfbQbPNjYV25VmbT7A5d3Bv5OENu/4aaaFfibEgiWuz0SdM+G/E549kK3P0l4mkNrNhFfxoiLlXIK/sS6siY+WvCPi5KmN7URIGRKNXKpUPQTZLg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by AS8PR04MB7879.eurprd04.prod.outlook.com (2603:10a6:20b:2a4::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.29; Tue, 12 Nov 2024 10:06:31 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%5]) with mapi id 15.20.8137.027; Tue, 12 Nov 2024 10:06:31 +0000 From: Liu Ying To: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, marex@denx.de Subject: [PATCH v6 5/7] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "pix" clock rate Date: Tue, 12 Nov 2024 18:05:45 +0800 Message-Id: <20241112100547.2908497-6-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112100547.2908497-1-victor.liu@nxp.com> References: <20241112100547.2908497-1-victor.liu@nxp.com> X-ClientProxiedBy: SG2PR02CA0025.apcprd02.prod.outlook.com (2603:1096:3:18::13) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|AS8PR04MB7879:EE_ X-MS-Office365-Filtering-Correlation-Id: f8d9f606-ab08-4baa-e834-08dd0301ae42 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|7416014|376014|366016|38350700014; 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This may filter modes out whose pixel clock rates cannot be supported by the pixel clock tree. For example, when the pixel clock is derived from the i.MX8MP video_pll1_out clock and video_pll1_out clock rate is 1.0395GHz, mode 720x576p@50Hz with 27MHz pixel clock rate will be filtered out in LDB split mode because the PLL clock rate does satisfy the "ldb" clock rate(27MHz * 3.5 = 94.5MHz) with 11 division ratio while it cannot satisfy the "pix" clock rate with 38.5 division ratio(only integer division ratio is supported). Signed-off-by: Liu Ying --- v6: * New patch. drivers/gpu/drm/bridge/fsl-ldb.c | 38 +++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index d9436ff9ccc3..035a3ffb4b3b 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -86,7 +87,8 @@ struct fsl_ldb { struct device *dev; struct drm_bridge bridge; struct drm_bridge *next_bridge; - struct clk *clk; + struct clk *clk_ldb; + struct clk *clk_pixel; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; bool ch0_enabled; @@ -176,15 +178,15 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, mode = &crtc_state->adjusted_mode; requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - clk_set_rate(fsl_ldb->clk, requested_link_freq); + clk_set_rate(fsl_ldb->clk_ldb, requested_link_freq); - configured_link_freq = clk_get_rate(fsl_ldb->clk); + configured_link_freq = clk_get_rate(fsl_ldb->clk_ldb); if (configured_link_freq != requested_link_freq) dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", configured_link_freq, requested_link_freq); - clk_prepare_enable(fsl_ldb->clk); + clk_prepare_enable(fsl_ldb->clk_ldb); /* Program LDB_CTRL */ reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | @@ -237,7 +239,7 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); - clk_disable_unprepare(fsl_ldb->clk); + clk_disable_unprepare(fsl_ldb->clk_ldb); } #define MAX_INPUT_SEL_FORMATS 1 @@ -269,15 +271,21 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { + unsigned long link_freq, pclk_rate, rounded_pclk_rate; struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - unsigned long link_freq; if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) return MODE_CLOCK_HIGH; /* Validate "ldb" clock rate. */ link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - if (link_freq != clk_round_rate(fsl_ldb->clk, link_freq)) + if (link_freq != clk_round_rate(fsl_ldb->clk_ldb, link_freq)) + return MODE_NOCLOCK; + + /* Validate pixel clock rate. */ + pclk_rate = mode->clock * HZ_PER_KHZ; + rounded_pclk_rate = clk_round_rate(fsl_ldb->clk_pixel, pclk_rate); + if (rounded_pclk_rate != pclk_rate) return MODE_NOCLOCK; return MODE_OK; @@ -297,7 +305,7 @@ static const struct drm_bridge_funcs funcs = { static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *remote1, *remote2; + struct device_node *remote0, *remote1, *remote2; struct fsl_ldb *fsl_ldb; int dual_link; @@ -313,9 +321,16 @@ static int fsl_ldb_probe(struct platform_device *pdev) fsl_ldb->bridge.funcs = &funcs; fsl_ldb->bridge.of_node = dev->of_node; - fsl_ldb->clk = devm_clk_get(dev, "ldb"); - if (IS_ERR(fsl_ldb->clk)) - return PTR_ERR(fsl_ldb->clk); + fsl_ldb->clk_ldb = devm_clk_get(dev, "ldb"); + if (IS_ERR(fsl_ldb->clk_ldb)) + return PTR_ERR(fsl_ldb->clk_ldb); + + /* Get pixel clock from display controller's OF node. */ + remote0 = of_graph_get_remote_node(dev->of_node, 0, 0); + fsl_ldb->clk_pixel = of_clk_get_by_name(remote0, "pix"); + of_node_put(remote0); + if (IS_ERR(fsl_ldb->clk_pixel)) + return PTR_ERR(fsl_ldb->clk_pixel); fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); if (IS_ERR(fsl_ldb->regmap)) @@ -375,6 +390,7 @@ static void fsl_ldb_remove(struct platform_device *pdev) struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); drm_bridge_remove(&fsl_ldb->bridge); + clk_put(fsl_ldb->clk_pixel); } static const struct of_device_id fsl_ldb_match[] = {