diff mbox series

clk:sophgo:clk-cv18xx-pll: Remove uninitialized u32 parameter and variable

Message ID 20241113025318.3667350-1-ragavendra.bn@gmail.com (mailing list archive)
State Changes Requested, archived
Headers show
Series clk:sophgo:clk-cv18xx-pll: Remove uninitialized u32 parameter and variable | expand

Commit Message

Ragavendra Nov. 13, 2024, 2:53 a.m. UTC 
Updating the detected value to 0 in the ipll_find_rate and removing it from the method parameters as it does not depend on external input. Updating the calls to ipll_find_rate as well and removing the u32 val variable from ipll_determine_rate.

Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com>
---
 drivers/clk/sophgo/clk-cv18xx-pll.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

Comments

kernel test robot Nov. 13, 2024, 9:39 a.m. UTC | #1 
Hi Ragavendra,

kernel test robot noticed the following build errors:

[auto build test ERROR on sophgo/for-next]
[also build test ERROR on sophgo/fixes linus/master v6.12-rc7 next-20241112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ragavendra/clk-sophgo-clk-cv18xx-pll-Remove-uninitialized-u32-parameter-and-variable/20241113-105536
base:   https://github.com/sophgo/linux.git for-next
patch link:    https://lore.kernel.org/r/20241113025318.3667350-1-ragavendra.bn%40gmail.com
patch subject: [PATCH] clk:sophgo:clk-cv18xx-pll: Remove uninitialized u32 parameter and variable
config: i386-buildonly-randconfig-005-20241113 (https://download.01.org/0day-ci/archive/20241113/202411131735.aLFcuMe3-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241113/202411131735.aLFcuMe3-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411131735.aLFcuMe3-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/clk/sophgo/clk-cv18xx-pll.c: In function 'ipll_find_rate':
>> drivers/clk/sophgo/clk-cv18xx-pll.c:80:18: error: 'value' undeclared (first use in this function)
      80 |                 *value = detected;
         |                  ^~~~~
   drivers/clk/sophgo/clk-cv18xx-pll.c:80:18: note: each undeclared identifier is reported only once for each function it appears in


vim +/value +80 drivers/clk/sophgo/clk-cv18xx-pll.c

80fd61ec46124e Inochi Amaoto 2024-03-09  46  
d666c0d9d14eb5 Ragavendra    2024-11-12  47  
80fd61ec46124e Inochi Amaoto 2024-03-09  48  static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
d666c0d9d14eb5 Ragavendra    2024-11-12  49  			  unsigned long prate, unsigned long *rate)
80fd61ec46124e Inochi Amaoto 2024-03-09  50  {
80fd61ec46124e Inochi Amaoto 2024-03-09  51  	unsigned long best_rate = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  52  	unsigned long trate = *rate;
80fd61ec46124e Inochi Amaoto 2024-03-09  53  	unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  54  	unsigned long pre, div, post;
d666c0d9d14eb5 Ragavendra    2024-11-12  55  	u32 detected = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  56  	unsigned long tmp;
80fd61ec46124e Inochi Amaoto 2024-03-09  57  
80fd61ec46124e Inochi Amaoto 2024-03-09  58  	for_each_pll_limit_range(pre, &limit->pre_div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  59  		for_each_pll_limit_range(div, &limit->div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  60  			for_each_pll_limit_range(post, &limit->post_div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  61  				tmp = ipll_calc_rate(prate, pre, div, post);
80fd61ec46124e Inochi Amaoto 2024-03-09  62  
80fd61ec46124e Inochi Amaoto 2024-03-09  63  				if (tmp > trate)
80fd61ec46124e Inochi Amaoto 2024-03-09  64  					continue;
80fd61ec46124e Inochi Amaoto 2024-03-09  65  
80fd61ec46124e Inochi Amaoto 2024-03-09  66  				if ((trate - tmp) < (trate - best_rate)) {
80fd61ec46124e Inochi Amaoto 2024-03-09  67  					best_rate = tmp;
80fd61ec46124e Inochi Amaoto 2024-03-09  68  					pre_div_sel = pre;
80fd61ec46124e Inochi Amaoto 2024-03-09  69  					div_sel = div;
80fd61ec46124e Inochi Amaoto 2024-03-09  70  					post_div_sel = post;
80fd61ec46124e Inochi Amaoto 2024-03-09  71  				}
80fd61ec46124e Inochi Amaoto 2024-03-09  72  			}
80fd61ec46124e Inochi Amaoto 2024-03-09  73  		}
80fd61ec46124e Inochi Amaoto 2024-03-09  74  	}
80fd61ec46124e Inochi Amaoto 2024-03-09  75  
80fd61ec46124e Inochi Amaoto 2024-03-09  76  	if (best_rate) {
80fd61ec46124e Inochi Amaoto 2024-03-09  77  		detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09  78  		detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09  79  		detected = PLL_SET_DIV_SEL(detected, div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09 @80  		*value = detected;
80fd61ec46124e Inochi Amaoto 2024-03-09  81  		*rate = best_rate;
80fd61ec46124e Inochi Amaoto 2024-03-09  82  		return 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  83  	}
80fd61ec46124e Inochi Amaoto 2024-03-09  84  
80fd61ec46124e Inochi Amaoto 2024-03-09  85  	return -EINVAL;
80fd61ec46124e Inochi Amaoto 2024-03-09  86  }
80fd61ec46124e Inochi Amaoto 2024-03-09  87
kernel test robot Nov. 13, 2024, 10 a.m. UTC | #2 
Hi Ragavendra,

kernel test robot noticed the following build errors:

[auto build test ERROR on sophgo/for-next]
[also build test ERROR on sophgo/fixes linus/master v6.12-rc7 next-20241112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ragavendra/clk-sophgo-clk-cv18xx-pll-Remove-uninitialized-u32-parameter-and-variable/20241113-105536
base:   https://github.com/sophgo/linux.git for-next
patch link:    https://lore.kernel.org/r/20241113025318.3667350-1-ragavendra.bn%40gmail.com
patch subject: [PATCH] clk:sophgo:clk-cv18xx-pll: Remove uninitialized u32 parameter and variable
config: arm-randconfig-001-20241113 (https://download.01.org/0day-ci/archive/20241113/202411131750.bsCkQYb6-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 592c0fe55f6d9a811028b5f3507be91458ab2713)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241113/202411131750.bsCkQYb6-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411131750.bsCkQYb6-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/clk/sophgo/clk-cv18xx-pll.c:80:4: error: use of undeclared identifier 'value'
      80 |                 *value = detected;
         |                  ^
   1 error generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for MODVERSIONS
   Depends on [n]: MODULES [=y] && !COMPILE_TEST [=y]
   Selected by [y]:
   - RANDSTRUCT_FULL [=y] && (CC_HAS_RANDSTRUCT [=y] || GCC_PLUGINS [=n]) && MODULES [=y]


vim +/value +80 drivers/clk/sophgo/clk-cv18xx-pll.c

80fd61ec46124e Inochi Amaoto 2024-03-09  46  
d666c0d9d14eb5 Ragavendra    2024-11-12  47  
80fd61ec46124e Inochi Amaoto 2024-03-09  48  static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
d666c0d9d14eb5 Ragavendra    2024-11-12  49  			  unsigned long prate, unsigned long *rate)
80fd61ec46124e Inochi Amaoto 2024-03-09  50  {
80fd61ec46124e Inochi Amaoto 2024-03-09  51  	unsigned long best_rate = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  52  	unsigned long trate = *rate;
80fd61ec46124e Inochi Amaoto 2024-03-09  53  	unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  54  	unsigned long pre, div, post;
d666c0d9d14eb5 Ragavendra    2024-11-12  55  	u32 detected = 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  56  	unsigned long tmp;
80fd61ec46124e Inochi Amaoto 2024-03-09  57  
80fd61ec46124e Inochi Amaoto 2024-03-09  58  	for_each_pll_limit_range(pre, &limit->pre_div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  59  		for_each_pll_limit_range(div, &limit->div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  60  			for_each_pll_limit_range(post, &limit->post_div) {
80fd61ec46124e Inochi Amaoto 2024-03-09  61  				tmp = ipll_calc_rate(prate, pre, div, post);
80fd61ec46124e Inochi Amaoto 2024-03-09  62  
80fd61ec46124e Inochi Amaoto 2024-03-09  63  				if (tmp > trate)
80fd61ec46124e Inochi Amaoto 2024-03-09  64  					continue;
80fd61ec46124e Inochi Amaoto 2024-03-09  65  
80fd61ec46124e Inochi Amaoto 2024-03-09  66  				if ((trate - tmp) < (trate - best_rate)) {
80fd61ec46124e Inochi Amaoto 2024-03-09  67  					best_rate = tmp;
80fd61ec46124e Inochi Amaoto 2024-03-09  68  					pre_div_sel = pre;
80fd61ec46124e Inochi Amaoto 2024-03-09  69  					div_sel = div;
80fd61ec46124e Inochi Amaoto 2024-03-09  70  					post_div_sel = post;
80fd61ec46124e Inochi Amaoto 2024-03-09  71  				}
80fd61ec46124e Inochi Amaoto 2024-03-09  72  			}
80fd61ec46124e Inochi Amaoto 2024-03-09  73  		}
80fd61ec46124e Inochi Amaoto 2024-03-09  74  	}
80fd61ec46124e Inochi Amaoto 2024-03-09  75  
80fd61ec46124e Inochi Amaoto 2024-03-09  76  	if (best_rate) {
80fd61ec46124e Inochi Amaoto 2024-03-09  77  		detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09  78  		detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09  79  		detected = PLL_SET_DIV_SEL(detected, div_sel);
80fd61ec46124e Inochi Amaoto 2024-03-09 @80  		*value = detected;
80fd61ec46124e Inochi Amaoto 2024-03-09  81  		*rate = best_rate;
80fd61ec46124e Inochi Amaoto 2024-03-09  82  		return 0;
80fd61ec46124e Inochi Amaoto 2024-03-09  83  	}
80fd61ec46124e Inochi Amaoto 2024-03-09  84  
80fd61ec46124e Inochi Amaoto 2024-03-09  85  	return -EINVAL;
80fd61ec46124e Inochi Amaoto 2024-03-09  86  }
80fd61ec46124e Inochi Amaoto 2024-03-09  87
Inochi Amaoto Nov. 13, 2024, 10:32 a.m. UTC | #3 
On Tue, Nov 12, 2024 at 06:53:18PM -0800, Ragavendra wrote:
> Updating the detected value to 0 in the ipll_find_rate and removing it from the method parameters as it does not depend on external input. Updating the calls to ipll_find_rate as well and removing the u32 val variable from ipll_determine_rate.
> 

You must break into lines with maximum 74 chars.

You title is weird, a more suitable example is
"clk: sophgo: Remove uninitialized variable for CV1800 PLL"

> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com>
> ---
>  drivers/clk/sophgo/clk-cv18xx-pll.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
> index 29e24098bf5f..57981a08fd5f 100644
> --- a/drivers/clk/sophgo/clk-cv18xx-pll.c
> +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
> @@ -44,15 +44,15 @@ static unsigned long ipll_recalc_rate(struct clk_hw *hw,
>  			      PLL_GET_POST_DIV_SEL(value));
>  }
>  
> +
>  static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
> -			  unsigned long prate, unsigned long *rate,
> -			  u32 *value)
> +			  unsigned long prate, unsigned long *rate)

This break the original logic since the value is used in the caller,
and I see nothing improved.

>  {
>  	unsigned long best_rate = 0;
>  	unsigned long trate = *rate;
>  	unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
>  	unsigned long pre, div, post;
> -	u32 detected = *value;
> +	u32 detected = 0;
>  	unsigned long tmp;
>  
>  	for_each_pll_limit_range(pre, &limit->pre_div) {
> @@ -87,11 +87,10 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
>  
>  static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
>  {
> -	u32 val;
>  	struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
>  
>  	return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
> -			      &req->rate, &val);
> +			      &req->rate);
>  }
>  
>  static void pll_get_mode_ctrl(unsigned long div_sel,
> @@ -134,7 +133,7 @@ static int ipll_set_rate(struct clk_hw *hw, unsigned long rate,
>  	unsigned long flags;
>  	struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
>  
> -	ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected);
> +	ipll_find_rate(pll->pll_limit, parent_rate, &rate);
>  	pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected),
>  			  ipll_check_mode_ctrl_restrict,
>  			  pll->pll_limit, &detected);
> -- 
> 2.46.1
> 

See the kernel test bot log.

Regards,
Inochi
diff mbox series

Patch

diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
index 29e24098bf5f..57981a08fd5f 100644
--- a/drivers/clk/sophgo/clk-cv18xx-pll.c
+++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
@@ -44,15 +44,15 @@  static unsigned long ipll_recalc_rate(struct clk_hw *hw,
 			      PLL_GET_POST_DIV_SEL(value));
 }
 
+
 static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
-			  unsigned long prate, unsigned long *rate,
-			  u32 *value)
+			  unsigned long prate, unsigned long *rate)
 {
 	unsigned long best_rate = 0;
 	unsigned long trate = *rate;
 	unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
 	unsigned long pre, div, post;
-	u32 detected = *value;
+	u32 detected = 0;
 	unsigned long tmp;
 
 	for_each_pll_limit_range(pre, &limit->pre_div) {
@@ -87,11 +87,10 @@  static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
 
 static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 {
-	u32 val;
 	struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
 
 	return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
-			      &req->rate, &val);
+			      &req->rate);
 }
 
 static void pll_get_mode_ctrl(unsigned long div_sel,
@@ -134,7 +133,7 @@  static int ipll_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long flags;
 	struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
 
-	ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected);
+	ipll_find_rate(pll->pll_limit, parent_rate, &rate);
 	pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected),
 			  ipll_check_mode_ctrl_restrict,
 			  pll->pll_limit, &detected);