From patchwork Wed Nov 13 02:59:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ragavendra B.N." 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Updating the calls to ipll_find_rate as well and removing the u32 val variable from ipll_determine_rate. Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Ragavendra Nagraj --- drivers/clk/sophgo/clk-cv18xx-pll.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - u32 val; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); return ipll_find_rate(pll->pll_limit, req->best_parent_rate, - &req->rate, &val); + &req->rate); } static void pll_get_mode_ctrl(unsigned long div_sel, @@ -134,7 +133,7 @@ static int ipll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long flags; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); - ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected); + ipll_find_rate(pll->pll_limit, parent_rate, &rate); pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected), ipll_check_mode_ctrl_restrict, pll->pll_limit, &detected); diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c index 29e24098bf5f..57981a08fd5f 100644 --- a/drivers/clk/sophgo/clk-cv18xx-pll.c +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c @@ -44,15 +44,15 @@ static unsigned long ipll_recalc_rate(struct clk_hw *hw, PLL_GET_POST_DIV_SEL(value)); } static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, - unsigned long prate, unsigned long *rate, - u32 *value) + unsigned long prate, unsigned long *rate) { unsigned long best_rate = 0; unsigned long trate = *rate; unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; unsigned long pre, div, post; - u32 detected = *value; + u32 detected = 0; unsigned long tmp; for_each_pll_limit_range(pre, &limit->pre_div) { @@ -87,11 +87,10 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,