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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432d54e2f2esm25664165e9.1.2024.11.13.05.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 05:36:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, lgirdwood@gmail.com, broonie@kernel.org, magnus.damm@gmail.com, linus.walleij@linaro.org, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-gpio@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 22/25] arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node Date: Wed, 13 Nov 2024 15:35:37 +0200 Message-Id: <20241113133540.2005850-23-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241113133540.2005850-1-claudiu.beznea.uj@bp.renesas.com> References: <20241113133540.2005850-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add versa3 clock generator node. It provides the clocks for the Ethernet PHY, PCIe, audio devices. Signed-off-by: Claudiu Beznea Reviewed-by: Biju Das --- Changes in v3: - none Changes in v2: - none .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 2ed01d391554..6e58d47d85b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -92,6 +92,12 @@ vcc_sdhi2: regulator2 { gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; #if SW_CONFIG3 == SW_ON @@ -152,6 +158,30 @@ &extal_clk { &i2c1 { status = "okay"; + + versa3: clock-generator@68 { + compatible = "renesas,5l35023"; + reg = <0x68>; + clocks = <&x3_clk>; + #clock-cells = <1>; + assigned-clocks = <&versa3 0>, + <&versa3 1>, + <&versa3 2>, + <&versa3 3>, + <&versa3 4>, + <&versa3 5>; + assigned-clock-rates = <24000000>, + <12288000>, + <11289600>, + <25000000>, + <100000000>, + <100000000>; + renesas,settings = [ + 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27 + 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86 + a0 80 30 30 9c + ]; + }; }; #if SW_CONFIG2 == SW_ON