| Message ID | 20241113184617.3745423-1-ragavendra.bn@gmail.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | clk:sophgo: Remove uninitialized variable for CV1800 PLL | expand |
Hi, Ragavendra, This patch should be revision for another https://lore.kernel.org/linux-clk/20241113025947.3670504-1-ragavendra.bn@gmail.com, right? If so you need add version info in the patch title and changelogs etc. Please read https://www.kernel.org/doc/html/latest/process/submitting-patches.html#the-canonical-patch-format carefully and re-post the patch. Kindly reminder, better declare dropping of this patch email and repost v2. Thanks, Chen On 2024/11/14 2:46, Ragavendra wrote: > Updating the detected value to 0 in the ipll_find_rate and removing it > from the method parameters as it does not depend on external input. > Updating the calls to ipll_find_rate as well and removing the u32 val > variable from ipll_determine_rate. > > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") > Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> > --- > drivers/clk/sophgo/clk-cv18xx-pll.c | 11 ++++------- > 1 file changed, 4 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c > index 29e24098bf5f..350195d4ac46 100644 > --- a/drivers/clk/sophgo/clk-cv18xx-pll.c > +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c > @@ -45,14 +45,13 @@ static unsigned long ipll_recalc_rate(struct clk_hw *hw, > } > > static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, > - unsigned long prate, unsigned long *rate, > - u32 *value) > + unsigned long prate, unsigned long *rate) > { > unsigned long best_rate = 0; > unsigned long trate = *rate; > unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; > unsigned long pre, div, post; > - u32 detected = *value; > + u32 detected = 0; > unsigned long tmp; > > for_each_pll_limit_range(pre, &limit->pre_div) { > @@ -77,7 +76,6 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, > detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel); > detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel); > detected = PLL_SET_DIV_SEL(detected, div_sel); > - *value = detected; > *rate = best_rate; > return 0; > } > @@ -87,11 +85,10 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, > > static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > { > - u32 val; > struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); > > return ipll_find_rate(pll->pll_limit, req->best_parent_rate, > - &req->rate, &val); > + &req->rate); > } > > static void pll_get_mode_ctrl(unsigned long div_sel, > @@ -134,7 +131,7 @@ static int ipll_set_rate(struct clk_hw *hw, unsigned long rate, > unsigned long flags; > struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); > > - ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected); > + ipll_find_rate(pll->pll_limit, parent_rate, &rate); > pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected), > ipll_check_mode_ctrl_restrict, > pll->pll_limit, &detected);
diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c index 29e24098bf5f..350195d4ac46 100644 --- a/drivers/clk/sophgo/clk-cv18xx-pll.c +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c @@ -45,14 +45,13 @@ static unsigned long ipll_recalc_rate(struct clk_hw *hw, } static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, - unsigned long prate, unsigned long *rate, - u32 *value) + unsigned long prate, unsigned long *rate) { unsigned long best_rate = 0; unsigned long trate = *rate; unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; unsigned long pre, div, post; - u32 detected = *value; + u32 detected = 0; unsigned long tmp; for_each_pll_limit_range(pre, &limit->pre_div) { @@ -77,7 +76,6 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel); detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel); detected = PLL_SET_DIV_SEL(detected, div_sel); - *value = detected; *rate = best_rate; return 0; } @@ -87,11 +85,10 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - u32 val; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); return ipll_find_rate(pll->pll_limit, req->best_parent_rate, - &req->rate, &val); + &req->rate); } static void pll_get_mode_ctrl(unsigned long div_sel, @@ -134,7 +131,7 @@ static int ipll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long flags; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); - ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected); + ipll_find_rate(pll->pll_limit, parent_rate, &rate); pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected), ipll_check_mode_ctrl_restrict, pll->pll_limit, &detected);
Updating the detected value to 0 in the ipll_find_rate and removing it from the method parameters as it does not depend on external input. Updating the calls to ipll_find_rate as well and removing the u32 val variable from ipll_determine_rate. Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> --- drivers/clk/sophgo/clk-cv18xx-pll.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-)