diff mbox series

[RFC,2/3] clk: amlogic: axg-audio: synchronize *_audio_hw_clks and *_clk_regmaps arrays

Message ID 20241114162926.3356551-3-jan.dakinevich@salutedevices.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series Make several simplification of axg-audio driver | expand

Commit Message

Jan Dakinevich Nov. 14, 2024, 4:29 p.m. UTC 
To simplify review, synchronize the content and order of clocks listed
in these arrays.

Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
 drivers/clk/meson/axg-audio.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 05a72a199ebd..5d2901b2a964 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -1095,6 +1095,8 @@  static struct clk_hw *g12a_audio_hw_clks[] = {
 	[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
 	[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
 	[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
+	[AUD_CLKID_TORAM]		= &toram.hw,
+	[AUD_CLKID_EQDRC]		= &eqdrc.hw,
 	[AUD_CLKID_TOP]			= &axg_aud_top,
 };
 
@@ -1428,6 +1430,9 @@  static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&spdifout_clk_sel,
 	&spdifout_clk_div,
 	&spdifout_clk,
+	&spdifout_b_clk_sel,
+	&spdifout_b_clk_div,
+	&spdifout_b_clk,
 	&spdifin_clk_sel,
 	&spdifin_clk_div,
 	&spdifin_clk,
@@ -1508,9 +1513,6 @@  static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&tdmout_a_lrclk,
 	&tdmout_b_lrclk,
 	&tdmout_c_lrclk,
-	&spdifout_b_clk_sel,
-	&spdifout_b_clk_div,
-	&spdifout_b_clk,
 	&g12a_tdm_mclk_pad_0,
 	&g12a_tdm_mclk_pad_1,
 	&g12a_tdm_lrclk_pad_0,
@@ -1565,6 +1567,9 @@  static struct clk_regmap *const sm1_clk_regmaps[] = {
 	&spdifout_clk_sel,
 	&spdifout_clk_div,
 	&spdifout_clk,
+	&spdifout_b_clk_sel,
+	&spdifout_b_clk_div,
+	&spdifout_b_clk,
 	&spdifin_clk_sel,
 	&spdifin_clk_div,
 	&spdifin_clk,
@@ -1645,9 +1650,6 @@  static struct clk_regmap *const sm1_clk_regmaps[] = {
 	&tdmout_a_lrclk,
 	&tdmout_b_lrclk,
 	&tdmout_c_lrclk,
-	&spdifout_b_clk_sel,
-	&spdifout_b_clk_div,
-	&spdifout_b_clk,
 	&sm1_tdm_mclk_pad_0,
 	&sm1_tdm_mclk_pad_1,
 	&sm1_tdm_lrclk_pad_0,