From patchwork Mon Nov 18 08:04:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13878245 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 868ED14D2BD; Mon, 18 Nov 2024 08:05:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731917125; cv=none; b=Qzj/vb2Cm9qhnRU6FYDR/cn+nm5sie0TxSCjdubnq8gvdRAnwKcAWsOC/JhGRpUfZOdp/CVlN8iNdSMK+3TjGkabFCY8V5S3Cxcg4ZgCNKAprfZcPOUXDQwFPBFrDHgxUIHknJaTCxBBNSGdjyaddxQg7rHUXV7iyeaQhobeVn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731917125; c=relaxed/simple; bh=e1YpwgPease7P3QoEBiAarKX0rKC/e+5uSyT0oTexTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eUUHZnzWAtk9ZJWS4LjGMOchhwWLvqKqnpd9aFMbrY+TCTnO7fvWZS5USIeT6W3EpnOhBZSFQaK5pZVghQaqlP6uVjiTGv6hmFsdzQS1COvMfeFRlI/owMqnL6+KFHok5Z1uK/uS4dSkxU4u/bLkbWlTSkimMD8Hqktht80xy1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vGoUTvxz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vGoUTvxz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1384EC4CECC; Mon, 18 Nov 2024 08:05:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731917125; bh=e1YpwgPease7P3QoEBiAarKX0rKC/e+5uSyT0oTexTI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vGoUTvxz9IGKU3BZk5iDZ7t1++zljRrGDajdtKpOzIPi2A/KGJNcGsZpFxB6fT+PS uPdnMRa76Tw8t4FFED9+4qgmOG099avagGVmWWWiww5Lg6tdPw5RqtfNzzUOf3oKlP JaQ8+mnlLYFHHLVrhLbnb27CvM9sUZ8szKBWPtS0okoRFD89DTrYUXwGIb/llH+6P9 xTpUP9fPyp/PXPbz4E1kAFbrSShbbklq2TxViiN8F8v9AA7tTaCcqh0EWKVZb1exnF mTL6kTqFcQC7Svl6PZWiKlIoXvEVQMh2A7gDhygvsfEIi0vez/Bv4aE455JoJi7V9A fpwV5LljfNUpg== From: Lorenzo Bianconi Date: Mon, 18 Nov 2024 09:04:54 +0100 Subject: [PATCH v4 2/6] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241118-pcie-en7581-fixes-v4-2-24bb61703ad7@kernel.org> References: <20241118-pcie-en7581-fixes-v4-0-24bb61703ad7@kernel.org> In-Reply-To: <20241118-pcie-en7581-fixes-v4-0-24bb61703ad7@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 4d1c797a32c236faf79428eb8a83708e9c4f21d8..3cfcb45d31508142d28d338ff213f70de9b4e608 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -948,12 +948,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -966,17 +960,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_assert(pcie->mac_reset);