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[80.181.61.65]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436611fc762sm16679975e9.11.2024.12.19.04.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 04:19:28 -0800 (PST) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH v3 3/4] clk: en7523: Rework clock handling for different clock numbers Date: Thu, 19 Dec 2024 13:18:52 +0100 Message-ID: <20241219121902.16339-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241219121902.16339-1-ansuelsmth@gmail.com> References: <20241219121902.16339-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Airoha EN7581 SoC have additional clock compared to EN7523 but current driver permits to only support up to EN7523 clock numbers. To handle this, rework the clock handling and permit to declare the clocks number in match_data and alloca clk_data based on the compatible match_data. Signed-off-by: Christian Marangi --- Changes v3: - Rework num_clocks for en7523 Changes v2: - Add this patch drivers/clk/clk-en7523.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 495c0d607c7d..596847446b14 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -75,6 +75,7 @@ struct en_rst_data { }; struct en_clk_soc_data { + u32 num_clocks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); @@ -504,8 +505,6 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat u32 rate; int i; - clk_data->num = EN7523_NUM_CLOCKS; - for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; @@ -587,8 +586,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat hw = en7523_register_pcie_clk(dev, base); clk_data->hws[EN7523_CLK_PCIE] = hw; - - clk_data->num = EN7523_NUM_CLOCKS; } static int en7523_reset_update(struct reset_controller_dev *rcdev, @@ -702,21 +699,24 @@ static int en7523_clk_probe(struct platform_device *pdev) struct clk_hw_onecell_data *clk_data; int r; + soc_data = device_get_match_data(&pdev->dev); + clk_data = devm_kzalloc(&pdev->dev, - struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + struct_size(clk_data, hws, soc_data->num_clocks), GFP_KERNEL); if (!clk_data) return -ENOMEM; - soc_data = device_get_match_data(&pdev->dev); r = soc_data->hw_init(pdev, clk_data); if (r) return r; + clk_data->num = soc_data->num_clocks; return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } static const struct en_clk_soc_data en7523_data = { + .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1, .pcie_ops = { .is_enabled = en7523_pci_is_enabled, .prepare = en7523_pci_prepare, @@ -726,6 +726,8 @@ static const struct en_clk_soc_data en7523_data = { }; static const struct en_clk_soc_data en7581_data = { + /* We increment num_clocks by 1 to account for additional PCIe clock */ + .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops = { .is_enabled = en7581_pci_is_enabled, .enable = en7581_pci_enable,