From patchwork Tue Dec 31 06:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian Hu X-Patchwork-Id: 13923648 Received: from mail-sh.amlogic.com (unknown [58.32.228.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE056175D39; Tue, 31 Dec 2024 06:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=58.32.228.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735625771; cv=none; b=uOMez0jyVtZgQDFcgk7sN6w0Gbu+IaG36y9asYTbWL/iF5Q54GIFe9A67zi2bYqQEll9OmM0p+I6uy0aGOG2qJdg76sKUvEcC/u7V42jKF71mX6/icJWEikjCL9yW8sivGm8V7QHXj5qvBlAT1d0PdNO2T01fWbjbJg9zUkFV+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735625771; c=relaxed/simple; bh=qJCY4QK2JUKY85r/c1NnFhQzgfZPuLZYfn9Ak2HQblk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sD9IyYNWjXdE9nR3UmjOK4Vu7DHjBmOmHv1rppqmVHIhH7cu9p6b/bYSt6IdmeCEk/1+GxvpKm5f5u4WbJ5Ctw1MHsDF/eYJmdO/bRwUoKKNFu7IeseFUAm37zoltKQBWXAJ+PPT75qiFuvxkEdNETpGCcigotlT/E7cgY0JwvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=58.32.228.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Tue, 31 Dec 2024 14:00:51 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller Date: Tue, 31 Dec 2024 14:00:43 +0800 Message-ID: <20241231060047.2298871-2-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231060047.2298871-1-jian.hu@amlogic.com> References: <20241231060047.2298871-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,t7-pll-clkc.yaml | 115 ++++++++++++++++++ .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 +++++++++ 2 files changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml new file mode 100644 index 000000000000..f90e6021d298 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 PLL Clock Control Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + - Xianwei Zhao + +properties: + compatible: + enum: + - amlogic,t7-pll-gp0 + - amlogic,t7-pll-gp1 + - amlogic,t7-pll-hifi + - amlogic,t7-pll-pcie + - amlogic,t7-mpll + - amlogic,t7-pll-hdmi + - amlogic,t7-pll-mclk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,t7-pll-gp0 + - amlogic,t7-pll-gp1 + - amlogic,t7-pll-hifi + - amlogic,t7-pll-pcie + - amlogic,t7-mpll + - amlogic,t7-pll-hdmi + then: + properties: + clocks: + items: + - description: pll input oscillator gate + + clock-names: + items: + - const: input + + - if: + properties: + compatible: + contains: + enum: + - amlogic,t7-pll-mclk + then: + properties: + clocks: + items: + - description: mclk pll input oscillator gate + - description: 24M oscillator input clock source for mclk_sel_0 + - description: fix 50Mhz input clock source for mclk_sel_0 + + clock-names: + items: + - const: input + - const: mclk_in0 + - const: mclk_in1 + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + gp0:clock-controller@8080 { + compatible = "amlogic,t7-pll-gp0"; + reg = <0 0x8080 0 0x20>; + clocks = <&scmi_clk 2>; + clock-names = "input"; + #clock-cells = <1>; + }; + + mclk:clock-controller@8300 { + compatible = "amlogic,t7-pll-mclk"; + reg = <0 0x8300 0 0x18>; + clocks = <&scmi_clk 2>, + <&xtal>, + <&scmi_clk 31>; + clock-names = "input", "mclk_in0", "mclk_in1"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h new file mode 100644 index 000000000000..e88c342028db --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#ifndef __T7_PLL_CLKC_H +#define __T7_PLL_CLKC_H + +/* GP0 */ +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 + +/* GP1 */ +#define CLKID_GP1_PLL_DCO 0 +#define CLKID_GP1_PLL 1 + +/* HIFI */ +#define CLKID_HIFI_PLL_DCO 0 +#define CLKID_HIFI_PLL 1 + +/* PCIE */ +#define CLKID_PCIE_PLL_DCO 0 +#define CLKID_PCIE_PLL_DCO_DIV2 1 +#define CLKID_PCIE_PLL_OD 2 +#define CLKID_PCIE_PLL 3 + +/* MPLL */ +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 + +/* HDMI */ +#define CLKID_HDMI_PLL_DCO 0 +#define CLKID_HDMI_PLL_OD 1 +#define CLKID_HDMI_PLL 2 + +/* MCLK */ +#define CLKID_MCLK_PLL_DCO 0 +#define CLKID_MCLK_PRE 1 +#define CLKID_MCLK_PLL 2 +#define CLKID_MCLK_0_SEL 3 +#define CLKID_MCLK_0_DIV2 4 +#define CLKID_MCLK_0_PRE 5 +#define CLKID_MCLK_0 6 +#define CLKID_MCLK_1_SEL 7 +#define CLKID_MCLK_1_DIV2 8 +#define CLKID_MCLK_1_PRE 9 +#define CLKID_MCLK_1 10 + +#endif /* __T7_PLL_CLKC_H */