| Message ID | 20250102163700.759712-3-rohit.visavalia@amd.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | dt-bindings: clock: xilinx: Update VCU bindings | expand |
On 02/01/2025 17:36, Rohit Visavalia wrote: > Convert AMD (Xilinx) VCU bindings to yaml format. > ... > + > +properties: > + compatible: > + items: > + - enum: > + - xlnx,vcu > + - xlnx,vcu-logicoreip-1.0 > + > + reg: > + description: > + The base offset and size of the VCU_PL_SLCR register space. Drop description, redundant. > + minItems: 1 There is no code like this. maxItems instead. Please use example-schema or other recently reviewed bindings as starting point. > + > + clocks: > + description: List of clock specifiers Drop description. > + items: > + - description: pll ref clocksource > + - description: aclk Original binding said different order. Mention change in commit msg with explanation why. Best regards, Krzysztof
Hi Krzysztof, Thanks for the review. >-----Original Message----- >From: Krzysztof Kozlowski <krzk@kernel.org> >Sent: Thursday, January 2, 2025 11:56 PM >To: Visavalia, Rohit <rohit.visavalia@amd.com>; mturquette@baylibre.com; >sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org >Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux- >kernel@vger.kernel.org >Subject: Re: [PATCH 2/3] dt-bindings: clock: xilinx: Convert VCU bindings to >dtschema > >On 02/01/2025 17:36, Rohit Visavalia wrote: >> Convert AMD (Xilinx) VCU bindings to yaml format. >> > > >... > >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - xlnx,vcu >> + - xlnx,vcu-logicoreip-1.0 >> + >> + reg: >> + description: >> + The base offset and size of the VCU_PL_SLCR register space. > >Drop description, redundant. I will take care in v2 patch series. > >> + minItems: 1 > >There is no code like this. maxItems instead. Please use example-schema or other >recently reviewed bindings as starting point. I will update in v2 patch. >> + >> + clocks: >> + description: List of clock specifiers > >Drop description. I will remove in v2 patch series. > >> + items: >> + - description: pll ref clocksource >> + - description: aclk > >Original binding said different order. Mention change in commit msg with >explanation why. I will update commit msg in v2 patch. > >Best regards, >Krzysztof Thanks Rohit
diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt b/Documentation/devicetree/bindings/clock/xlnx,vcu.txt deleted file mode 100644 index 2417b13ba468..000000000000 --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt +++ /dev/null @@ -1,26 +0,0 @@ -LogicoreIP designed compatible with Xilinx ZYNQ family. -------------------------------------------------------- - -General concept ---------------- - -LogicoreIP design to provide the isolation between processing system -and programmable logic. Also provides the list of register set to configure -the frequency. - -Required properties: -- compatible: shall be one of: - "xlnx,vcu" - "xlnx,vcu-logicoreip-1.0" -- reg : The base offset and size of the VCU_PL_SLCR register space. -- clocks: phandle for aclk and pll_ref clocksource -- clock-names: The identification string, "aclk", is always required for - the axi clock. "pll_ref" is required for pll. -Example: - - xlnx_vcu: vcu@a0040000 { - compatible = "xlnx,vcu-logicoreip-1.0"; - reg = <0x0 0xa0040000 0x0 0x1000>; - clocks = <&si570_1>, <&clkc 71>; - clock-names = "pll_ref", "aclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml new file mode 100644 index 000000000000..bdb14594c40b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: LogicoreIP designed compatible with Xilinx ZYNQ family. + +maintainers: + - Rohit Visavalia <rohit.visavalia@amd.com> + +description: + LogicoreIP design to provide the isolation between processing system + and programmable logic. Also provides the list of register set to configure + the frequency. + +properties: + compatible: + items: + - enum: + - xlnx,vcu + - xlnx,vcu-logicoreip-1.0 + + reg: + description: + The base offset and size of the VCU_PL_SLCR register space. + minItems: 1 + + clocks: + description: List of clock specifiers + items: + - description: pll ref clocksource + - description: aclk + + clock-names: + items: + - const: pll_ref + - const: aclk + +required: + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga { + #address-cells = <2>; + #size-cells = <2>; + xlnx_vcu: vcu@a0040000 { + compatible = "xlnx,vcu-logicoreip-1.0"; + reg = <0x0 0xa0040000 0x0 0x1000>; + clocks = <&si570_1>, <&clkc 71>; + clock-names = "pll_ref", "aclk"; + }; + };
Convert AMD (Xilinx) VCU bindings to yaml format. Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com> --- .../devicetree/bindings/clock/xlnx,vcu.txt | 26 --------- .../devicetree/bindings/clock/xlnx,vcu.yaml | 58 +++++++++++++++++++ 2 files changed, 58 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.txt create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml