[6/6] arm64: defconfig: Enable RZ/G3S thermal

Message ID	20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
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Headers	show Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07D971FCCF4 for <linux-clk@vger.kernel.org>; Fri, 3 Jan 2025 16:38:41 +0000 (UTC) From: Claudiu <claudiu.beznea@tuxon.dev> To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 6/6] arm64: defconfig: Enable RZ/G3S thermal Date: Fri, 3 Jan 2025 18:38:05 +0200 Message-ID: <20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	thermal: renesas: Add support for RZ/G3S \| expand [0/6] thermal: renesas: Add support for RZ/G3S [1/6] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP [2/6] thermal: of: Export non-devres helper to register/unregister thermal zone [3/6] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit [4/6] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC [5/6] arm64: dts: renesas: r9a08g045: Add TSU node [6/6] arm64: defconfig: Enable RZ/G3S thermal

Message ID

20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com (mailing list archive)

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Not Applicable, archived

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: rafael@kernel.org,
	daniel.lezcano@linaro.org,
	rui.zhang@intel.com,
	lukasz.luba@arm.com,
	robh@kernel.org,
	krzk+dt@kernel.org,
	conor+dt@kernel.org,
	geert+renesas@glider.be,
	magnus.damm@gmail.com,
	mturquette@baylibre.com,
	sboyd@kernel.org,
	p.zabel@pengutronix.de,
	ulf.hansson@linaro.org
Cc: claudiu.beznea@tuxon.dev,
	linux-pm@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-clk@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 6/6] arm64: defconfig: Enable RZ/G3S thermal
Date: Fri,  3 Jan 2025 18:38:05 +0200
Message-ID: <20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com>
References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com>
Precedence: bulk
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Series

thermal: renesas: Add support for RZ/G3S | expand

Commit Message

Claudiu Beznea Jan. 3, 2025, 4:38 p.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable the CONFIG_RZG3S_THERMAL flag for the RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dfa5c8d5b658..576a544b8c79 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -706,6 +706,7 @@  CONFIG_ROCKCHIP_THERMAL=m
 CONFIG_RCAR_THERMAL=y
 CONFIG_RCAR_GEN3_THERMAL=y
 CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3S_THERMAL=m
 CONFIG_ARMADA_THERMAL=y
 CONFIG_MTK_THERMAL=m
 CONFIG_MTK_LVTS_THERMAL=m

[6/6] arm64: defconfig: Enable RZ/G3S thermal

Commit Message

Patch