From patchwork Wed Jan 8 09:50:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930453 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3769417C20F; Wed, 8 Jan 2025 09:51:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329863; cv=none; b=YI30DG9Ir4DumhN1jWyRpKpPm1Sluh0efo23DG00TAcY9l1GAX9QH+LkNcLZ9A3p4u16NYDeOaEpbo1iQY8NdxysgIWncjzqn5HjwseIrhZe8/d14e5MTUeYbUFqo9+EYsdhknLp9BUKFdTkWh3wdjRZxsLoD0tfjKS1tfmrPqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329863; c=relaxed/simple; bh=29cWk1BMgfLD5wAcay/Bq/fTMXy4oV5VbyKl8GHHLpg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pNIoHwln25+cNvMh6G0mZZPQKtPfQOEKipK/QILsIG+epa6HdmXTZ2SFnbDTNn2q2ffS50QvapcnIIRPQ5uQlQ4IpBwR/2U4bEGduQzF4XPlBJUMjMXHC3mgN1+rgNcAcYIKQYWReruzTNEl/hbiOUKNId9MGHuYnuJxZxpumqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fV76BW8a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fV76BW8a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A64EC4CEE0; Wed, 8 Jan 2025 09:51:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329862; bh=29cWk1BMgfLD5wAcay/Bq/fTMXy4oV5VbyKl8GHHLpg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fV76BW8aIOK3acC6C9OCKVX5dMEOa0FTArVi9tby3Nw5mT82wg4yiEtahhiSN/Pb3 QOVy1df/KF6aq8y3L73kxNnHrwpIIi2ZW/L6tcw4K69QuBwb+wuEA7pJYw96NfY7li H9j8kIn4XVGKxYXGPokyuS1kRBJ9vG1e9AbxJGeSkmBPvh0Qujm12beYbpOpSlKZog GGFvAKKJZslHFUUGs7lWP9Mtb2VwgA48IFjXKdcVmRLO85lOE3uOgJR/J73QXw9c3p 7poqPkCp/r1TzrnhCsR21TXqaXndwIogALKvY+4X24XrGhtVNizxs2YY8SZIRymAew 76/PAAfXOcplw== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:40 +0100 Subject: [PATCH v6 1/5] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index be52e3a123abd0d0086f9f1a603e3abaa18f319f..886d458df40d009424c2ae6f1564f51a669643ad 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -945,12 +945,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -963,17 +957,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);