From patchwork Wed Jan 8 09:50:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930454 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07F241E0DC3; Wed, 8 Jan 2025 09:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329866; cv=none; b=TUWtVFIzZTM6MxFdO1YES2k4CImb7uL15oMjvwVul7j3iJasChyE2C5nX9juV0H2Yd5ZWGWRHa3oDJfbhCZ7WnIu7KeAkvuuck69bvm0YnuuiUuUF2aYtFEYEgyfpLDa/MfCPkuhfrzwoGs1X4O6IXL50asOxUMV2D+5ZLu1lgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329866; c=relaxed/simple; bh=sSr7jnmf2lp/4KRHdrUAbnv/WR37msyTvdSzhf1tJ8Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ip7iLjVAD7OtqaBf+so1SZvzrn0KCDOAmRzK+0QOwSl1GIE8Co/zbxcQ0AwqVdTe4sKt15Si8uZi3Do88OSSbGI6UrB0xSEiNyoNFrv61Sj8gr1zD0oif7QlrBlIFe2I5yagqeLLjJ9zphi1rgtvbkiowQ9z4bezM6HzXJvbk8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FhpNwLdx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FhpNwLdx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46AB0C4CEE0; Wed, 8 Jan 2025 09:51:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329865; bh=sSr7jnmf2lp/4KRHdrUAbnv/WR37msyTvdSzhf1tJ8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FhpNwLdxaKGsKIUHU1csO8vSGF2k8DXxx5RcT9VlytWKkeOH/ddhgLnwshaJY++hc 7fV09VmGUy2rIYZPgFV/Lf6ENx6LPN7/0PWatYRxwUj9hQUPYQpTJ3vUJT7g4Zm8fL KvtEcULOfm72xr2hWqWqhh6QYOb/HC0ZysDm0iOyGIIFLE3F0y4OxxAx9jM3COLb1A wjOcfU3hdAdpPWDvHr5gKB904jH4xxgMJEmvqI4aUq26GGT0uiC9HeJDboBE9BnZRL s9HFqH1j0u8Igf2ISoz/d+k3VMZdBHbP44gmGlkvVk71yQ4AxqJi8DDUhAJ2tFxsSS uJvs/IEY3C/fg== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:41 +0100 Subject: [PATCH v6 2/5] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-2-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, the reset_control_bulk_assert() for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 886d458df40d009424c2ae6f1564f51a669643ad..4ce2b9d0dcd54e44cb645603d81865d26b2c8f23 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -125,6 +125,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -913,9 +915,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) u32 val; /* - * Wait for the time needed to complete the bulk assert in - * mtk_pcie_setup for EN7581 SoC. + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + + /* Wait for the time needed to complete the reset lines assert. */ mdelay(PCIE_EN7581_RESET_TIME_MS); err = phy_init(pcie->phy); @@ -982,6 +989,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1066,14 +1082,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie);