From patchwork Fri Feb 14 02:13:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jiebing chen via B4 Relay X-Patchwork-Id: 13974354 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCED32F24; Fri, 14 Feb 2025 02:13:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739499223; cv=none; b=I2sRuSYIck9JgyTrymm2kOfLoefqcnas84FDQq4Py8ebUhQf0tWCl0FnbWM9AmX1KtVIGoYscM+AHb3x0zpVfItEpSihvImCKkFHxYlZQt1K63VR+yd4o5uqNeZvtsRSPgJogB7a+P2JW95MfAT8XPtFKKs5GVuNg5go6+zxdws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739499223; c=relaxed/simple; bh=J1c0zfW3w2qqbwBk6grELOoOJWOzilKRY8yWea8SsbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mLDWN4mvrawQDNUdZBfPMpSVFp4vsYGhHBWUL6y5q85X1LW2td9EemiRu5Dy2Vnu04tKkkd4b+2d+8O6qzg40UpksCmaFj0CMEFImD7FHhCpXmd6T1QDxwQxGauf9qxHy3KhyD6QyUUmaA/yjPtUxqOoDpFtbIcmFMR0zbyB/HQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DtcUWs2D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DtcUWs2D" Received: by smtp.kernel.org (Postfix) with ESMTPS id 55A06C4CEE5; Fri, 14 Feb 2025 02:13:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739499223; bh=J1c0zfW3w2qqbwBk6grELOoOJWOzilKRY8yWea8SsbU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DtcUWs2DuPlCTCSNl34WF6fUcKJD1Ami9nRaNqnHRHCDcVASDEBZcr2pWt4DfV4ev uxXcaBcqxmJPG2QoL8xUOlyhtvxtgdhzwUCqD6Dztdt0CH4+mN5MVLbeMcCR7kuEqs bHTdHV3Xqn6tPr/cZZHIW9yc3tyiKODMK60f5DhN/3EVz+xPQomZmRJn5jGOo6aK/X bdU99JrIqt3M3XS7QVxaDmjPzsBMBWKnHiA2entsdniAJRY6nDYIf9gofvKxwiVR9v 0ga0RAvLuPHZtChs/oYrzWEXuagd0P0RCxsidAz652fBacoARP0wwSJaufFMU3wIoL PbV83ERgCcV0Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BDEC021A4; Fri, 14 Feb 2025 02:13:43 +0000 (UTC) From: jiebing chen via B4 Relay Date: Fri, 14 Feb 2025 10:13:40 +0800 Subject: [PATCH v2 1/5] dt-bindings: clock: axg-audio: Add mclk and sclk pad for s4 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250214-audio_drvier-v2-1-37881fa37c9e@amlogic.com> References: <20250214-audio_drvier-v2-0-37881fa37c9e@amlogic.com> In-Reply-To: <20250214-audio_drvier-v2-0-37881fa37c9e@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739499221; l=2710; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=TXC0nl0bF7ijEJ/f38+2QuSrF8LeB5NHcRgGAcnuK24=; b=hAMjhlWqZaRMxN531Yg+WGONAd/WY5kKkSD06NC7KGnMbzlciO0K80ublViD+xrTkfXqM8JwG p75Eq0MFLDoDJKe4Vm/Wx/FTn0L6cGgslDabJaKnkzKXY/41ZfN7WYd X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen add the s4 audio power domain, add the mclk pad, sclk pad and lrclk pad clock id for s4 Signed-off-by: jiebing chen --- .../bindings/clock/amlogic,axg-audio-clkc.yaml | 18 ++++++++++++++++++ include/dt-bindings/clock/axg-audio-clkc.h | 11 +++++++++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml index fd7982dd4ceab82389167079c2258a9acff51a76..364783c6f7572b09d57de2b35d33adb7bcf7db18 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -21,6 +21,7 @@ properties: - amlogic,axg-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc + - amlogic,s4-audio-clkc '#clock-cells': const: 1 @@ -100,6 +101,9 @@ properties: resets: description: internal reset line + power-domains: + description: audio controller power + required: - compatible - '#clock-cells' @@ -116,12 +120,26 @@ allOf: enum: - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc + - amlogic,s4-audio-clkc then: required: - '#reset-cells' else: properties: '#reset-cells': false + - if: + properties: + compatible: + contains: + enum: + - amlogic,s4-audio-clkc + then: + required: + - power-domains + + else: + properties: + power-domains: false additionalProperties: false diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index 607f23b83fa7287fe0403682ebf827e2df26a1ce..75dde05343d1fa74304ee21c9ec0541a8f51b15e 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -162,5 +162,16 @@ #define AUD_CLKID_EARCRX_DMAC_SEL 182 #define AUD_CLKID_EARCRX_DMAC_DIV 183 #define AUD_CLKID_EARCRX_DMAC 184 +#define AUD_CLKID_TDM_MCLK_PAD0_SEL 185 +#define AUD_CLKID_TDM_MCLK_PAD1_SEL 186 +#define AUD_CLKID_TDM_MCLK_PAD0_DIV 187 +#define AUD_CLKID_TDM_MCLK_PAD1_DIV 188 +#define AUD_CLKID_TDM_MCLK_PAD2 189 +#define AUD_CLKID_TDM_MCLK_PAD2_SEL 190 +#define AUD_CLKID_TDM_MCLK_PAD2_DIV 191 +#define AUD_CLKID_TDM_SCLK_PAD3 192 +#define AUD_CLKID_TDM_SCLK_PAD4 193 +#define AUD_CLKID_TDM_LRCLK_PAD3 194 +#define AUD_CLKID_TDM_LRCLK_PAD4 195 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */