| Message ID | 20250214125359.5204-4-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | clk: sunxi-ng: add A523 clock support | expand |
On Fri, Feb 14, 2025 at 8:56 PM Andre Przywara <andre.przywara@arm.com> wrote: > > So far our sunxi clock instantiation macros set the required flags > depending on the clock type, but the new "dual divider MP clock" > requires us to pass that piece of information in by the user. > > Add a new wrapper macro that allows to specify a "features" field, to > allow marking those dual-divider clocks accordingly. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > drivers/clk/sunxi-ng/ccu_mp.h | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h > index e235fdfde2d36..687bd2ec798e2 100644 > --- a/drivers/clk/sunxi-ng/ccu_mp.h > +++ b/drivers/clk/sunxi-ng/ccu_mp.h > @@ -100,11 +100,12 @@ struct ccu_mp { > _muxshift, _muxwidth, \ > 0, _flags) > > -#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ > +#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \ > _mshift, _mwidth, \ > _pshift, _pwidth, \ > _muxshift, _muxwidth, \ > - _gate, _flags) \ > + _gate, _flags, \ > + _features) \ > struct ccu_mp _struct = { \ > .enable = _gate, \ > .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ > @@ -112,13 +113,25 @@ struct ccu_mp { > .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ > .common = { \ > .reg = _reg, \ > + .features = _features, \ > .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ > _parents, \ > - &ccu_mp_ops, \ > + &ccu_mp_ops,\ Accidental change? Otherwise, Reviewed-by: Chen-Yu Tsai <wens@csie.org> > _flags), \ > } \ > } > > +#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ > + _mshift, _mwidth, \ > + _pshift, _pwidth, \ > + _muxshift, _muxwidth, \ > + _gate, _flags) \ > + SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \ > + _reg, _mshift, _mwidth, \ > + _pshift, _pwidth, \ > + _muxshift, _muxwidth, \ > + _gate, _flags, 0) > + > #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ > _mshift, _mwidth, \ > _pshift, _pwidth, \ > -- > 2.46.3 >
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h index e235fdfde2d36..687bd2ec798e2 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.h +++ b/drivers/clk/sunxi-ng/ccu_mp.h @@ -100,11 +100,12 @@ struct ccu_mp { _muxshift, _muxwidth, \ 0, _flags) -#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ +#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \ _mshift, _mwidth, \ _pshift, _pwidth, \ _muxshift, _muxwidth, \ - _gate, _flags) \ + _gate, _flags, \ + _features) \ struct ccu_mp _struct = { \ .enable = _gate, \ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ @@ -112,13 +113,25 @@ struct ccu_mp { .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ .common = { \ .reg = _reg, \ + .features = _features, \ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ _parents, \ - &ccu_mp_ops, \ + &ccu_mp_ops,\ _flags), \ } \ } +#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _pshift, _pwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \ + _reg, _mshift, _mwidth, \ + _pshift, _pwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags, 0) + #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ _mshift, _mwidth, \ _pshift, _pwidth, \
So far our sunxi clock instantiation macros set the required flags depending on the clock type, but the new "dual divider MP clock" requires us to pass that piece of information in by the user. Add a new wrapper macro that allows to specify a "features" field, to allow marking those dual-divider clocks accordingly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/clk/sunxi-ng/ccu_mp.h | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)