@@ -45,6 +45,7 @@ properties:
- allwinner,sun50i-h6-r-ccu
- allwinner,sun50i-h616-ccu
- allwinner,sun50i-h616-r-ccu
+ - allwinner,sun55i-a523-ccu
- allwinner,suniv-f1c100s-ccu
- nextthing,gr8-ccu
@@ -106,6 +107,7 @@ else:
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h616-ccu
+ - allwinner,sun55i-a523-ccu
then:
properties:
new file mode 100644
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
+#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
+
+#define CLK_PLL_DDR0 0
+#define CLK_PLL_PERIPH0_4X 1
+#define CLK_PLL_PERIPH0_2X 2
+#define CLK_PLL_PERIPH0_800M 3
+#define CLK_PLL_PERIPH0_480M 4
+#define CLK_PLL_PERIPH0_600M 5
+#define CLK_PLL_PERIPH0_400M 6
+#define CLK_PLL_PERIPH0_300M 7
+#define CLK_PLL_PERIPH0_200M 8
+#define CLK_PLL_PERIPH0_160M 9
+#define CLK_PLL_PERIPH0_150M 10
+#define CLK_PLL_PERIPH1_4X 11
+#define CLK_PLL_PERIPH1_2X 12
+#define CLK_PLL_PERIPH1_800M 13
+#define CLK_PLL_PERIPH1_480M 14
+#define CLK_PLL_PERIPH1_600M 15
+#define CLK_PLL_PERIPH1_400M 16
+#define CLK_PLL_PERIPH1_300M 17
+#define CLK_PLL_PERIPH1_200M 18
+#define CLK_PLL_PERIPH1_160M 19
+#define CLK_PLL_PERIPH1_150M 20
+#define CLK_PLL_GPU 21
+#define CLK_PLL_VIDEO0_8X 22
+#define CLK_PLL_VIDEO0_4X 23
+#define CLK_PLL_VIDEO0_3X 24
+#define CLK_PLL_VIDEO1_8X 25
+#define CLK_PLL_VIDEO1_4X 26
+#define CLK_PLL_VIDEO1_3X 27
+#define CLK_PLL_VIDEO2_8X 28
+#define CLK_PLL_VIDEO2_4X 29
+#define CLK_PLL_VIDEO2_3X 30
+#define CLK_PLL_VIDEO3_8X 31
+#define CLK_PLL_VIDEO3_4X 32
+#define CLK_PLL_VIDEO3_3X 33
+#define CLK_PLL_VE 34
+#define CLK_PLL_AUDIO0_4X 35
+#define CLK_PLL_AUDIO0_2X 36
+#define CLK_PLL_AUDIO0 37
+#define CLK_PLL_AUDIO1 38
+#define CLK_PLL_AUDIO1_DIV2 39
+#define CLK_PLL_AUDIO1_DIV5 40
+#define CLK_PLL_NPU_4X 41
+#define CLK_PLL_NPU_2X 42
+#define CLK_PLL_NPU 43
+#define CLK_AHB 44
+#define CLK_APB0 45
+#define CLK_APB1 46
+#define CLK_MBUS 47
+#define CLK_DE 48
+#define CLK_BUS_DE 49
+#define CLK_DI 50
+#define CLK_BUS_DI 51
+#define CLK_G2D 52
+#define CLK_BUS_G2D 53
+#define CLK_GPU 54
+#define CLK_BUS_GPU 55
+#define CLK_CE 56
+#define CLK_BUS_CE 57
+#define CLK_BUS_CE_SYS 58
+#define CLK_VE 59
+#define CLK_BUS_VE 60
+#define CLK_BUS_DMA 61
+#define CLK_BUS_MSGBOX 62
+#define CLK_BUS_SPINLOCK 63
+#define CLK_HSTIMER0 64
+#define CLK_HSTIMER1 65
+#define CLK_HSTIMER2 66
+#define CLK_HSTIMER3 67
+#define CLK_HSTIMER4 68
+#define CLK_HSTIMER5 69
+#define CLK_BUS_HSTIMER 70
+#define CLK_BUS_DBG 71
+#define CLK_BUS_PWM0 72
+#define CLK_BUS_PWM1 73
+#define CLK_IOMMU 74
+#define CLK_BUS_IOMMU 75
+#define CLK_DRAM 76
+#define CLK_MBUS_DMA 77
+#define CLK_MBUS_VE 78
+#define CLK_MBUS_CE 79
+#define CLK_MBUS_TVIN 80
+#define CLK_MBUS_CSI 81
+#define CLK_BUS_DRAM 82
+#define CLK_NAND0 83
+#define CLK_NAND1 84
+#define CLK_BUS_NAND 85
+#define CLK_MMC0 86
+#define CLK_MMC1 87
+#define CLK_MMC2 88
+#define CLK_BUS_SYSDAP 89
+#define CLK_BUS_MMC0 90
+#define CLK_BUS_MMC1 91
+#define CLK_BUS_MMC2 92
+#define CLK_BUS_UART0 93
+#define CLK_BUS_UART1 94
+#define CLK_BUS_UART2 95
+#define CLK_BUS_UART3 96
+#define CLK_BUS_UART4 97
+#define CLK_BUS_UART5 98
+#define CLK_BUS_UART6 99
+#define CLK_BUS_UART7 100
+#define CLK_BUS_I2C0 101
+#define CLK_BUS_I2C1 102
+#define CLK_BUS_I2C2 103
+#define CLK_BUS_I2C3 104
+#define CLK_BUS_I2C4 105
+#define CLK_BUS_I2C5 106
+#define CLK_BUS_CAN 107
+#define CLK_SPI0 108
+#define CLK_SPI1 109
+#define CLK_SPI2 110
+#define CLK_SPIFC 111
+#define CLK_BUS_SPI0 112
+#define CLK_BUS_SPI1 113
+#define CLK_BUS_SPI2 114
+#define CLK_BUS_SPIFC 115
+#define CLK_EMAC0_25M 116
+#define CLK_EMAC1_25M 117
+#define CLK_BUS_EMAC0 118
+#define CLK_BUS_EMAC1 119
+#define CLK_IR_RX 120
+#define CLK_BUS_IR_RX 121
+#define CLK_IR_TX 122
+#define CLK_BUS_IR_TX 123
+#define CLK_GPADC0 124
+#define CLK_GPADC1 125
+#define CLK_BUS_GPADC0 126
+#define CLK_BUS_GPADC1 127
+#define CLK_BUS_THS 128
+#define CLK_USB_OHCI0 129
+#define CLK_USB_OHCI1 130
+#define CLK_BUS_OHCI0 131
+#define CLK_BUS_OHCI1 132
+#define CLK_BUS_EHCI0 133
+#define CLK_BUS_EHCI1 134
+#define CLK_BUS_OTG 135
+#define CLK_BUS_LRADC 136
+#define CLK_PCIE_AUX 137
+#define CLK_BUS_DPSS_TOP 138
+#define CLK_HDMI_24M 139
+#define CLK_HDMI_CEC_32K 140
+#define CLK_HDMI_CEC 141
+#define CLK_BUS_HDMI 142
+#define CLK_MIPI_DSI0 143
+#define CLK_MIPI_DSI1 144
+#define CLK_BUS_MIPI_DSI0 145
+#define CLK_BUS_MIPI_DSI1 146
+#define CLK_TCON_LCD0 147
+#define CLK_TCON_LCD1 148
+#define CLK_COMBOPHY_DSI0 149
+#define CLK_COMBOPHY_DSI1 150
+#define CLK_BUS_TCON_LCD0 151
+#define CLK_BUS_TCON_LCD1 152
+#define CLK_TCON_TV0 153
+#define CLK_TCON_TV1 154
+#define CLK_BUS_TCON_TV0 155
+#define CLK_BUS_TCON_TV1 156
+#define CLK_EDP 157
+#define CLK_BUS_EDP 158
+#define CLK_LEDC 159
+#define CLK_BUS_LEDC 160
+#define CLK_CSI_TOP 161
+#define CLK_CSI_MCLK0 162
+#define CLK_CSI_MCLK1 163
+#define CLK_CSI_MCLK2 164
+#define CLK_CSI_MCLK3 165
+#define CLK_BUS_CSI 166
+#define CLK_ISP 167
+#define CLK_DSP 168
+#define CLK_BUS_DSP_CFG 169
+#define CLK_FANOUT_24M 170
+#define CLK_FANOUT_12M 171
+#define CLK_FANOUT_16M 172
+#define CLK_FANOUT_25M 173
+#define CLK_FANOUT_32K 174
+#define CLK_FANOUT_27M 175
+#define CLK_FANOUT_PCLK 176
+#define CLK_FANOUT0 177
+#define CLK_FANOUT1 178
+#define CLK_FANOUT2 179
+
+#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
new file mode 100644
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
+#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
+
+#define RST_MBUS 0
+#define RST_BUS_NSI 1
+#define RST_BUS_DE 2
+#define RST_BUS_DI 3
+#define RST_BUS_G2D 4
+#define RST_BUS_SYS 5
+#define RST_BUS_GPU 6
+#define RST_BUS_CE 7
+#define RST_BUS_SYS_CE 8
+#define RST_BUS_VE 9
+#define RST_BUS_DMA 10
+#define RST_BUS_MSGBOX 11
+#define RST_BUS_SPINLOCK 12
+#define RST_BUS_CPUXTIMER 13
+#define RST_BUS_DBG 14
+#define RST_BUS_PWM0 15
+#define RST_BUS_PWM1 16
+#define RST_BUS_DRAM 17
+#define RST_BUS_NAND 18
+#define RST_BUS_MMC0 19
+#define RST_BUS_MMC1 20
+#define RST_BUS_MMC2 21
+#define RST_BUS_SYSDAP 22
+#define RST_BUS_UART0 23
+#define RST_BUS_UART1 24
+#define RST_BUS_UART2 25
+#define RST_BUS_UART3 26
+#define RST_BUS_UART4 27
+#define RST_BUS_UART5 28
+#define RST_BUS_UART6 29
+#define RST_BUS_UART7 30
+#define RST_BUS_I2C0 31
+#define RST_BUS_I2C1 32
+#define RST_BUS_I2C2 33
+#define RST_BUS_I2C3 34
+#define RST_BUS_I2C4 35
+#define RST_BUS_I2C5 36
+#define RST_BUS_CAN 37
+#define RST_BUS_SPI0 38
+#define RST_BUS_SPI1 39
+#define RST_BUS_SPI2 40
+#define RST_BUS_SPIFC 41
+#define RST_BUS_EMAC0 42
+#define RST_BUS_EMAC1 43
+#define RST_BUS_IR_RX 44
+#define RST_BUS_IR_TX 45
+#define RST_BUS_GPADC0 46
+#define RST_BUS_GPADC1 47
+#define RST_BUS_THS 48
+#define RST_USB_PHY0 49
+#define RST_USB_PHY1 50
+#define RST_BUS_OHCI0 51
+#define RST_BUS_OHCI1 52
+#define RST_BUS_EHCI0 53
+#define RST_BUS_EHCI1 54
+#define RST_BUS_OTG 55
+#define RST_BUS_3 56
+#define RST_BUS_LRADC 57
+#define RST_BUS_PCIE_USB3 58
+#define RST_BUS_DPSS_TOP 59
+#define RST_BUS_HDMI_MAIN 60
+#define RST_BUS_HDMI_SUB 61
+#define RST_BUS_MIPI_DSI0 62
+#define RST_BUS_MIPI_DSI1 63
+#define RST_BUS_TCON_LCD0 64
+#define RST_BUS_TCON_LCD1 65
+#define RST_BUS_TCON_LCD2 66
+#define RST_BUS_TCON_TV0 67
+#define RST_BUS_TCON_TV1 68
+#define RST_BUS_LVDS0 69
+#define RST_BUS_LVDS1 70
+#define RST_BUS_EDP 71
+#define RST_BUS_VIDEO_OUT0 72
+#define RST_BUS_VIDEO_OUT1 73
+#define RST_BUS_LEDC 74
+#define RST_BUS_CSI 75
+#define RST_BUS_ISP 76
+
+#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */