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Tue, 18 Feb 2025 14:27:23 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:18 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:47 +0530 Subject: [PATCH 2/5] clk: qcom: common: Add support to attach multiple power domains Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-2-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sZOxJA6fYnQb5lBszC5ag8aH77-x2TCK X-Proofpoint-ORIG-GUID: sZOxJA6fYnQb5lBszC5ag8aH77-x2TCK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=832 phishscore=0 spamscore=0 clxscore=1011 mlxscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 From: Taniya Das In the latest chipset clock controllers, multiple power domains can be required to access and configure the PLLs in probe. Therefore, add support for an API to attach to multiple power domains in the clock controller probe before configuring the PLLs. Signed-off-by: Taniya Das Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 12 ++++++++++++ drivers/clk/qcom/common.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..ec27f70b24bdec24edd2f6b3df0d766fc1cdcbf0 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -391,5 +391,17 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, } EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); +int qcom_cc_attach_pds(struct device *dev, struct qcom_cc_desc *desc) +{ + int ret; + + ret = devm_pm_domain_attach_list(dev, NULL, &desc->pd_list); + if (ret < 0 && ret != -EEXIST) + return ret; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_cc_attach_pds); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("QTI Common Clock module"); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 7ace5d7f5836aa81431153ba92d8f14f2ffe8147..45f1f53fb407d4600f5059b792564b68cd8c244d 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -38,6 +38,7 @@ struct qcom_cc_desc { const struct qcom_icc_hws_data *icc_hws; size_t num_icc_hws; unsigned int icc_first_node_id; + struct dev_pm_domain_list *pd_list; }; /** @@ -76,5 +77,6 @@ extern int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc); extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, const struct qcom_cc_desc *desc); +extern int qcom_cc_attach_pds(struct device *dev, struct qcom_cc_desc *desc); #endif