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[83.11.221.132]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac25d376342sm213104766b.106.2025.03.07.23.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 23:50:52 -0800 (PST) From: Artur Weber Date: Sat, 08 Mar 2025 08:50:44 +0100 Subject: [PATCH v3 6/9] clk: bcm21664: Add matching bus clocks for peripheral clocks Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250308-kona-bus-clock-v3-6-d6fb5bfc3b67@gmail.com> References: <20250308-kona-bus-clock-v3-0-d6fb5bfc3b67@gmail.com> In-Reply-To: <20250308-kona-bus-clock-v3-0-d6fb5bfc3b67@gmail.com> To: Michael Turquette , Stephen Boyd , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alex Elder , Stanislav Jakubek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741420241; l=4962; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=oquOoPMtK5XsMhLVUCejF4XDRVd+flbgwR9aw0XPHXc=; b=ZId+ES/3D+3LQyHOLlbBz3j3NcrC26QMWeXN5hJAb6Uil7SJvrN51sFxyVVvQJQvuBAEOe4eO tS9b5+53a9pAq2Ra8I8n/JyvMpiL1tMzp3dwrk3hqoF6ingJB92HRCo X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= Now that bus clock support has been implemented into the Broadcom Kona clock driver, add bus clocks corresponding to HUB_TIMER, SDIO, UART and BSC, as well as the USB OTG bus clock. Signed-off-by: Artur Weber --- Changes in v3: - Adapt to CLOCK_COUNT defines being moved Changes in v2: - Adapt to dropped prereq clocks --- drivers/clk/bcm/clk-bcm21664.c | 89 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm21664.c b/drivers/clk/bcm/clk-bcm21664.c index fa6e1649d6f5f459b63026109caea9e2f72e22dd..53fd46d97b6514ebe228a874c63cd2cccb8a0f55 100644 --- a/drivers/clk/bcm/clk-bcm21664.c +++ b/drivers/clk/bcm/clk-bcm21664.c @@ -41,7 +41,12 @@ static struct peri_clk_data hub_timer_data = { .trig = TRIGGER(0x0a40, 4), }; -#define BCM21664_AON_CCU_CLOCK_COUNT (BCM21664_AON_CCU_HUB_TIMER + 1) +static struct bus_clk_data hub_timer_apb_data = { + .gate = HW_SW_GATE(0x0414, 18, 3, 2), + .hyst = HYST(0x0414, 10, 11), +}; + +#define BCM21664_AON_CCU_CLOCK_COUNT (BCM21664_AON_CCU_HUB_TIMER_APB + 1) static struct ccu_data aon_ccu_data = { BCM21664_CCU_COMMON(aon, AON), @@ -52,6 +57,8 @@ static struct ccu_data aon_ccu_data = { .kona_clks = { [BCM21664_AON_CCU_HUB_TIMER] = KONA_CLK(aon, hub_timer, peri), + [BCM21664_AON_CCU_HUB_TIMER_APB] = + KONA_CLK(aon, hub_timer_apb, bus), [BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; @@ -126,7 +133,27 @@ static struct peri_clk_data sdio4_sleep_data = { .gate = HW_SW_GATE(0x0360, 18, 2, 3), }; -#define BCM21664_MASTER_CCU_CLOCK_COUNT (BCM21664_MASTER_CCU_SDIO4_SLEEP + 1) +static struct bus_clk_data sdio1_ahb_data = { + .gate = HW_SW_GATE(0x0358, 16, 0, 1), +}; + +static struct bus_clk_data sdio2_ahb_data = { + .gate = HW_SW_GATE(0x035c, 16, 0, 1), +}; + +static struct bus_clk_data sdio3_ahb_data = { + .gate = HW_SW_GATE(0x0364, 16, 0, 1), +}; + +static struct bus_clk_data sdio4_ahb_data = { + .gate = HW_SW_GATE(0x0360, 16, 0, 1), +}; + +static struct bus_clk_data usb_otg_ahb_data = { + .gate = HW_SW_GATE(0x0348, 16, 0, 1), +}; + +#define BCM21664_MASTER_CCU_CLOCK_COUNT (BCM21664_MASTER_CCU_USB_OTG_AHB + 1) static struct ccu_data master_ccu_data = { BCM21664_CCU_COMMON(master, MASTER), @@ -151,6 +178,16 @@ static struct ccu_data master_ccu_data = { KONA_CLK(master, sdio3_sleep, peri), [BCM21664_MASTER_CCU_SDIO4_SLEEP] = KONA_CLK(master, sdio4_sleep, peri), + [BCM21664_MASTER_CCU_SDIO1_AHB] = + KONA_CLK(master, sdio1_ahb, bus), + [BCM21664_MASTER_CCU_SDIO2_AHB] = + KONA_CLK(master, sdio2_ahb, bus), + [BCM21664_MASTER_CCU_SDIO3_AHB] = + KONA_CLK(master, sdio3_ahb, bus), + [BCM21664_MASTER_CCU_SDIO4_AHB] = + KONA_CLK(master, sdio4_ahb, bus), + [BCM21664_MASTER_CCU_USB_OTG_AHB] = + KONA_CLK(master, usb_otg_ahb, bus), [BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; @@ -231,7 +268,39 @@ static struct peri_clk_data bsc4_data = { .trig = TRIGGER(0x0afc, 19), }; -#define BCM21664_SLAVE_CCU_CLOCK_COUNT (BCM21664_SLAVE_CCU_BSC4 + 1) +static struct bus_clk_data uartb_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0400, 16, 0, 1), +}; + +static struct bus_clk_data uartb2_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0404, 16, 0, 1), +}; + +static struct bus_clk_data uartb3_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0408, 16, 0, 1), +}; + +static struct bus_clk_data bsc1_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), + .hyst = HYST(0x0458, 8, 9), +}; + +static struct bus_clk_data bsc2_apb_data = { + .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), + .hyst = HYST(0x045c, 8, 9), +}; + +static struct bus_clk_data bsc3_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0470, 16, 0, 1), + .hyst = HYST(0x0470, 8, 9), +}; + +static struct bus_clk_data bsc4_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0474, 16, 0, 1), + .hyst = HYST(0x0474, 8, 9), +}; + +#define BCM21664_SLAVE_CCU_CLOCK_COUNT (BCM21664_SLAVE_CCU_BSC4_APB + 1) static struct ccu_data slave_ccu_data = { BCM21664_CCU_COMMON(slave, SLAVE), @@ -254,6 +323,20 @@ static struct ccu_data slave_ccu_data = { KONA_CLK(slave, bsc3, peri), [BCM21664_SLAVE_CCU_BSC4] = KONA_CLK(slave, bsc4, peri), + [BCM21664_SLAVE_CCU_UARTB_APB] = + KONA_CLK(slave, uartb_apb, bus), + [BCM21664_SLAVE_CCU_UARTB2_APB] = + KONA_CLK(slave, uartb2_apb, bus), + [BCM21664_SLAVE_CCU_UARTB3_APB] = + KONA_CLK(slave, uartb3_apb, bus), + [BCM21664_SLAVE_CCU_BSC1_APB] = + KONA_CLK(slave, bsc1_apb, bus), + [BCM21664_SLAVE_CCU_BSC2_APB] = + KONA_CLK(slave, bsc2_apb, bus), + [BCM21664_SLAVE_CCU_BSC3_APB] = + KONA_CLK(slave, bsc3_apb, bus), + [BCM21664_SLAVE_CCU_BSC4_APB] = + KONA_CLK(slave, bsc4_apb, bus), [BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, };