diff mbox series

[v5,02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

Message ID 20250325160904.2688858-3-thierry.bultel.yh@bp.renesas.com (mailing list archive)
State Under Review
Headers show
Series None | expand

Commit Message

Thierry Bultel March 25, 2025, 4:08 p.m. UTC 
Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
Changes v4->v5:
  - Set reg minItems and maxItems defaults at top level
Changes v3->v4:
  - Handle maxItems and clocks names properly in schema. 
---
 .../bindings/clock/renesas,cpg-mssr.yaml      | 55 +++++++++++++------
 .../clock/renesas,r9a09g077-cpg-mssr.h        | 49 +++++++++++++++++
 2 files changed, 88 insertions(+), 16 deletions(-)
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

Comments

Krzysztof Kozlowski March 26, 2025, 7:49 a.m. UTC | #1 
On Tue, Mar 25, 2025 at 05:08:50PM +0100, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
> Changes v4->v5:
>   - Set reg minItems and maxItems defaults at top level
> Changes v3->v4:
>   - Handle maxItems and clocks names properly in schema. 


Can you start using b4 or send patchsets in standard way? No links to
previous versions in changelog and b4 diff does not work:

b4 diff '20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com'
Grabbing thread from lore.kernel.org/all/20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com/t.mbox.gz
Checking for older revisions
Grabbing search results from lore.kernel.org
  Added from v4: 14 patches
---
Analyzing 140 messages in the thread
Preparing fake-am for v4: dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC
ERROR: Could not fake-am version v4
---
Could not create fake-am range for lower series v4


> ---
>  .../bindings/clock/renesas,cpg-mssr.yaml      | 55 +++++++++++++------
>  .../clock/renesas,r9a09g077-cpg-mssr.h        | 49 +++++++++++++++++
>  2 files changed, 88 insertions(+), 16 deletions(-)
>  create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> index 77ce3615c65a..5181ff826dbe 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> @@ -52,9 +52,11 @@ properties:
>        - renesas,r8a779f0-cpg-mssr # R-Car S4-8
>        - renesas,r8a779g0-cpg-mssr # R-Car V4H
>        - renesas,r8a779h0-cpg-mssr # R-Car V4M
> +      - renesas,r9a09g077-cpg-mssr # RZ/T2H
>  
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
>  
>    clocks:
>      minItems: 1
> @@ -63,11 +65,6 @@ properties:
>    clock-names:
>      minItems: 1
>      maxItems: 2
> -    items:
> -      enum:
> -        - extal     # All
> -        - extalr    # Most R-Car Gen3 and RZ/G2
> -        - usb_extal # Most R-Car Gen2 and RZ/G1
>  
>    '#clock-cells':
>      description: |
> @@ -92,16 +89,6 @@ properties:
>        the datasheet.
>      const: 1
>  
> -if:
> -  not:
> -    properties:
> -      compatible:
> -        items:
> -          enum:
> -            - renesas,r7s9210-cpg-mssr
> -then:
> -  required:
> -    - '#reset-cells'
>  
>  required:
>    - compatible
> @@ -113,6 +100,42 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:

This goes befoer additionalProps. See example-schema.

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g077-cpg-mssr
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2

Missing constriants for clocks.

Best regards,
Krzysztof
Paul Barker March 26, 2025, 10:28 a.m. UTC | #2 
On 26/03/2025 07:49, Krzysztof Kozlowski wrote:
> On Tue, Mar 25, 2025 at 05:08:50PM +0100, Thierry Bultel wrote:
>> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
>>
>> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>> ---
>> Changes v4->v5:
>>   - Set reg minItems and maxItems defaults at top level
>> Changes v3->v4:
>>   - Handle maxItems and clocks names properly in schema. 
> 
> 
> Can you start using b4 or send patchsets in standard way? No links to
> previous versions in changelog and b4 diff does not work:
> 
> b4 diff '20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com'
> Grabbing thread from lore.kernel.org/all/20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com/t.mbox.gz
> Checking for older revisions
> Grabbing search results from lore.kernel.org
>   Added from v4: 14 patches
> ---
> Analyzing 140 messages in the thread
> Preparing fake-am for v4: dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC
> ERROR: Could not fake-am version v4
> ---
> Could not create fake-am range for lower series v4

Hi Krzysztof,

The above b4 command works for me. Which b4 version are you using and
which base tree do you have checked out?

FYI, this series now applies cleanly on top of tty-next as Geert's
patch [1] has been integrated.

[1]: https://lore.kernel.org/linux-renesas-soc/11c2eab45d48211e75d8b8202cce60400880fe55.1741114989.git.geert+renesas@glider.be/T/#u

Thanks,
Krzysztof Kozlowski March 26, 2025, 10:32 a.m. UTC | #3 
On 26/03/2025 11:28, Paul Barker wrote:
> On 26/03/2025 07:49, Krzysztof Kozlowski wrote:
>> On Tue, Mar 25, 2025 at 05:08:50PM +0100, Thierry Bultel wrote:
>>> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
>>>
>>> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>>> ---
>>> Changes v4->v5:
>>>   - Set reg minItems and maxItems defaults at top level
>>> Changes v3->v4:
>>>   - Handle maxItems and clocks names properly in schema. 
>>
>>
>> Can you start using b4 or send patchsets in standard way? No links to
>> previous versions in changelog and b4 diff does not work:
>>
>> b4 diff '20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com'
>> Grabbing thread from lore.kernel.org/all/20250325160904.2688858-1-thierry.bultel.yh@bp.renesas.com/t.mbox.gz
>> Checking for older revisions
>> Grabbing search results from lore.kernel.org
>>   Added from v4: 14 patches
>> ---
>> Analyzing 140 messages in the thread
>> Preparing fake-am for v4: dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC
>> ERROR: Could not fake-am version v4
>> ---
>> Could not create fake-am range for lower series v4
> 
> Hi Krzysztof,
> 
> The above b4 command works for me. Which b4 version are you using and
> which base tree do you have checked out?
> 
> FYI, this series now applies cleanly on top of tty-next as Geert's
> patch [1] has been integrated.
> 
> [1]: https://lore.kernel.org/linux-renesas-soc/11c2eab45d48211e75d8b8202cce60400880fe55.1741114989.git.geert+renesas@glider.be/T/#u
Latest b4 and latest next (next-20250321). I tried next-20250317 as well.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 77ce3615c65a..5181ff826dbe 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -52,9 +52,11 @@  properties:
       - renesas,r8a779f0-cpg-mssr # R-Car S4-8
       - renesas,r8a779g0-cpg-mssr # R-Car V4H
       - renesas,r8a779h0-cpg-mssr # R-Car V4M
+      - renesas,r9a09g077-cpg-mssr # RZ/T2H
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   clocks:
     minItems: 1
@@ -63,11 +65,6 @@  properties:
   clock-names:
     minItems: 1
     maxItems: 2
-    items:
-      enum:
-        - extal     # All
-        - extalr    # Most R-Car Gen3 and RZ/G2
-        - usb_extal # Most R-Car Gen2 and RZ/G1
 
   '#clock-cells':
     description: |
@@ -92,16 +89,6 @@  properties:
       the datasheet.
     const: 1
 
-if:
-  not:
-    properties:
-      compatible:
-        items:
-          enum:
-            - renesas,r7s9210-cpg-mssr
-then:
-  required:
-    - '#reset-cells'
 
 required:
   - compatible
@@ -113,6 +100,42 @@  required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-cpg-mssr
+    then:
+      properties:
+        reg:
+          minItems: 2
+        clock-names:
+          items:
+            - const: extal
+            - const: loco
+    else:
+      properties:
+        reg:
+          maxItems: 1
+        clock-names:
+          items:
+            enum:
+              - extal     # All
+              - extalr    # Most R-Car Gen3 and RZ/G2
+              - usb_extal # Most R-Car Gen2 and RZ/G1
+
+  - if:
+      not:
+        properties:
+          compatible:
+            items:
+              enum:
+                - renesas,r7s9210-cpg-mssr
+    then:
+      required:
+        - '#reset-cells'
+
 examples:
   - |
     cpg: clock-controller@e6150000 {
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
new file mode 100644
index 000000000000..27c9cdcdf7c8
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -0,0 +1,49 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CA55C0		0
+#define R9A09G077_CA55C1		1
+#define R9A09G077_CA55C2		2
+#define R9A09G077_CA55C3		3
+#define R9A09G077_SDHIHS		4
+#define R9A09G077_CLK_PLL1_ETH_PHY	5
+#define R9A09G077_CLK_OSC_ETH_PHY	6
+#define R9A09G077_CLK_ETHPHY		7
+#define R9A09G077_PCLKAH		8
+#define R9A09G077_PCLKAM		9
+#define R9A09G077_PCLKAL		10
+#define R9A09G077_CLK_SEL_ETH_PHY	11
+#define R9A09G077_DFI			12
+#define R9A09G077_PCLKH			13
+#define R9A09G077_PCLKM			14
+#define R9A09G077_PCLKL			15
+#define R9A09G077_PCLKGPTL		16
+#define R9A09G077_PCLKSHOST		17
+#define R9A09G077_PCLKRTC		18
+#define R9A09G077_USB			19
+#define R9A09G077_SPI0			20
+#define R9A09G077_SPI1			21
+#define R9A09G077_SPI2			22
+#define R9A09G077_SPI3			23
+#define R9A09G077_ETCLKA		24
+#define R9A09G077_ETCLKB		25
+#define R9A09G077_ETCLKC		26
+#define R9A09G077_ETCLKD		27
+#define R9A09G077_ETCLKE		28
+#define R9A09G077_ETHCLKE		29
+#define R9A09G077_ETHCLK_EXTAL		30
+#define R9A09G077_ETH_REFCLK		31
+#define R9A09G077_LCDC_CLKA		32
+#define R9A09G077_LCDC_CLKP		33
+#define R9A09G077_CA55			34
+#define R9A09G077_LCDC_CLKD		35
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */