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[11/15] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC

Message ID 20250326143945.82142-12-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Not Applicable, archived
Headers show
Series Add support for Renesas RZ/V2N SoC and EVK | expand

Commit Message

Prabhakar March 26, 2025, 2:39 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.

To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.

Also add `renesas,r9a09g056-pinctrl.h` header file which define pins
that will be used by the driver and board DTS files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  2 ++
 .../pinctrl/renesas,r9a09g056-pinctrl.h       | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h

Comments

Krzysztof Kozlowski March 27, 2025, 7:48 a.m. UTC | #1 
On 26/03/2025 15:39, Prabhakar wrote:
> +#define RZV2N_P3	3
> +#define RZV2N_P4	4
> +#define RZV2N_P5	5
> +#define RZV2N_P6	6
> +#define RZV2N_P7	7
> +#define RZV2N_P8	8
> +#define RZV2N_P9	9
> +#define RZV2N_PA	10
> +#define RZV2N_PB	11

Same comments as before - not useful to repeat the name.

It is the third patch in this patchset, which receives exactly the same
comments as given before.

I expect that given feedback somehow stays within group of contributions
or company in form of internal knowledge. Or just read other people's
patchset to learn from them and do not make the same mistakes.

> +
> +#define RZV2N_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
> +#define RZV2N_GPIO(port, pin)		RZG2L_GPIO(RZV2N_P##port, pin)

Not a binding. If you claim otherwise, point me to the line of driver
code using this binding.

Best regards,
Krzysztof
Prabhakar March 28, 2025, 3:05 p.m. UTC | #2 
Hi  Krzysztof,

Thank you for the review.

On Thu, Mar 27, 2025 at 7:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 26/03/2025 15:39, Prabhakar wrote:
> > +#define RZV2N_P3     3
> > +#define RZV2N_P4     4
> > +#define RZV2N_P5     5
> > +#define RZV2N_P6     6
> > +#define RZV2N_P7     7
> > +#define RZV2N_P8     8
> > +#define RZV2N_P9     9
> > +#define RZV2N_PA     10
> > +#define RZV2N_PB     11
>
> Same comments as before - not useful to repeat the name.
>
> It is the third patch in this patchset, which receives exactly the same
> comments as given before.
>
> I expect that given feedback somehow stays within group of contributions
> or company in form of internal knowledge. Or just read other people's
> patchset to learn from them and do not make the same mistakes.
>
For the RZ/V2H and RZ/G3E SoC similar changes were accepted, to keep
consistency with these SoCs this header file was added.

[0] https://lore.kernel.org/all/20241218192202.GA2184154-robh@kernel.org/

> > +
> > +#define RZV2N_PORT_PINMUX(b, p, f)   RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
> > +#define RZV2N_GPIO(port, pin)                RZG2L_GPIO(RZV2N_P##port, pin)
>
> Not a binding. If you claim otherwise, point me to the line of driver
> code using this binding.
>
Note, since OF data of V2H was mostly reused in the pinctrl driver due
to similarities there wasn't a need to include this header file in the
driver code. My intention here was to use this header file in DTS/I to
keep similarities. Maybe I'll create a
r9a09g056_variable_pin_cfg{} so that this header file gets included in
the driver.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 768bb3c2b456..5156d54b240b 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -27,6 +27,7 @@  properties:
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
               - renesas,r9a08g045-pinctrl # RZ/G3S
               - renesas,r9a09g047-pinctrl # RZ/G3E
+              - renesas,r9a09g056-pinctrl # RZ/V2N
               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 
       - items:
@@ -145,6 +146,7 @@  allOf:
           contains:
             enum:
               - renesas,r9a09g047-pinctrl
+              - renesas,r9a09g056-pinctrl
               - renesas,r9a09g057-pinctrl
     then:
       properties:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
new file mode 100644
index 000000000000..206bba07c288
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
@@ -0,0 +1,30 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2N SoC pinctrl bindings.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2N_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZV2N_P0	0
+#define RZV2N_P1	1
+#define RZV2N_P2	2
+#define RZV2N_P3	3
+#define RZV2N_P4	4
+#define RZV2N_P5	5
+#define RZV2N_P6	6
+#define RZV2N_P7	7
+#define RZV2N_P8	8
+#define RZV2N_P9	9
+#define RZV2N_PA	10
+#define RZV2N_PB	11
+
+#define RZV2N_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
+#define RZV2N_GPIO(port, pin)		RZG2L_GPIO(RZV2N_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__ */