| Message ID | 20250409-clk-cdce6214-v2-2-40b25b722ecb@pengutronix.de (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | clk: add support for TI CDCE6214 | expand |
On 09/04/2025 13:20, Sascha Hauer wrote: > The CDCE6214 is a Ultra-Low Power Clock Generator With One PLL, Four > Differential Outputs, Two Inputs, and Internal EEPROM. This patch adds > the device tree binding for this chip. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../devicetree/bindings/clock/ti,cdce6214.yaml | 167 +++++++++++++++++++++ > include/dt-bindings/clock/ti,cdce6214.h | 24 +++ > 2 files changed, 191 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml > new file mode 100644 > index 0000000000000..957e40403100d > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml > @@ -0,0 +1,167 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/ti,cdce6214.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI CDCE6214 programmable clock generator with PLL > + > +maintainers: > + - Sascha Hauer <s.hauer@pengutronix.de> > + > +description: > + Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, > + Two Inputs, and Internal EEPROM > + > + https://www.ti.com/product/CDCE6214 > + > +properties: > + compatible: > + enum: > + - ti,cdce6214 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 1 > + items: > + enum: [ priref, secref ] > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#clock-cells': > + const: 1 > + > +patternProperties: > + '^clk@[0-1]$': > + type: object > + description: > + optional child node that can be used to specify input pin parameters. The reg > + properties match the CDCE6214_CLK_* defines. > + > + additionalProperties: false > + > + properties: > + reg: > + description: > + clock input identifier. > + minimum: 0 > + maximum: 1 > + > + ti,clkin-fmt: > + description: | > + Clock input format. Available options are: > + 0 LVCMOS > + 1 XTAL > + 2 Differential > + $ref: /schemas/types.yaml#/definitions/uint32 Drop, that's not string. Make it readable for DTS users. > + minimum: 0 > + maximum: 2 > + > + ti,xo-cload-femtofarad: > + description: > + Selects load cap for XO in femto Farad (fF). Up to 9000fF > + $ref: /schemas/types.yaml#/definitions/uint32 Drop and use proper unit suffix from property-units in dtschema. > + minimum: 3000 > + maximum: 9000 > + > + ti,xo-bias-current-microampere: > + description: > + Bias current setting of the XO. > + $ref: /schemas/types.yaml#/definitions/uint32 Ditto > + minimum: 0 > + maximum: 1758 > + > + '^clk@[2-9]$': > + type: object > + description: > + optional child node that can be used to specify output pin parameters. The reg > + properties match the CDCE6214_CLK_* defines. > + > + additionalProperties: false > + > + properties: > + reg: > + description: > + clock output identifier. > + minimum: 2 > + maximum: 9 > + > + ti,clkout-fmt: > + description: | > + Clock input format. Available options are: > + 0 CMOS > + 1 LVDS > + 2 LP-HCSL Drop these three lines > + $ref: /schemas/types.yaml#/definitions/uint32 Drop, this is supposed to be string. enum: [ cmos, lvds, lp-hcsl ] > + minimum: 0 > + maximum: 2 > + > + ti,cmos-mode: > + description: | > + CMOS output mode. Available options are: > + 0 disabled > + 1 high polarity > + 2 low polarity > + first array entry is for the CMOSP pin, second for the CMOSN pin > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 2 > + maxItems: 2 > + items: > + maximum: 2 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + i2c { > + #address-cells = <1>; > + #size-cells = <0>; > + > + clock-generator@67 { > + compatible = "ti,cdce6214"; > + reg = <0x67>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + clocks = <&clock_ref25m>; > + clock-names = "secref"; > + > + clk@1 { > + reg = <1>; // CDCE6214_CLK_SECREF > + ti,clkin-fmt = <1>; // XTAL > + }; > + > + clk@3 { > + reg = <3>; // CDCE6214_CLK_OUT1 > + ti,clkout-fmt = <0>; // CMOS > + ti,cmos-mode = <1 2>; // CMOSP = highpol, CMOSN = lowpol Why do you need comments here? If you chosen magic numbers, it means they are readable by themself. If you need comments, then it is a sign they are not obvious and just go with the code I asked you - enum string. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml new file mode 100644 index 0000000000000..957e40403100d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,cdce6214.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CDCE6214 programmable clock generator with PLL + +maintainers: + - Sascha Hauer <s.hauer@pengutronix.de> + +description: + Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, + Two Inputs, and Internal EEPROM + + https://www.ti.com/product/CDCE6214 + +properties: + compatible: + enum: + - ti,cdce6214 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 1 + items: + enum: [ priref, secref ] + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#clock-cells': + const: 1 + +patternProperties: + '^clk@[0-1]$': + type: object + description: + optional child node that can be used to specify input pin parameters. The reg + properties match the CDCE6214_CLK_* defines. + + additionalProperties: false + + properties: + reg: + description: + clock input identifier. + minimum: 0 + maximum: 1 + + ti,clkin-fmt: + description: | + Clock input format. Available options are: + 0 LVCMOS + 1 XTAL + 2 Differential + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + + ti,xo-cload-femtofarad: + description: + Selects load cap for XO in femto Farad (fF). Up to 9000fF + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 3000 + maximum: 9000 + + ti,xo-bias-current-microampere: + description: + Bias current setting of the XO. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1758 + + '^clk@[2-9]$': + type: object + description: + optional child node that can be used to specify output pin parameters. The reg + properties match the CDCE6214_CLK_* defines. + + additionalProperties: false + + properties: + reg: + description: + clock output identifier. + minimum: 2 + maximum: 9 + + ti,clkout-fmt: + description: | + Clock input format. Available options are: + 0 CMOS + 1 LVDS + 2 LP-HCSL + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + + ti,cmos-mode: + description: | + CMOS output mode. Available options are: + 0 disabled + 1 high polarity + 2 low polarity + first array entry is for the CMOSP pin, second for the CMOSN pin + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + maximum: 2 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@67 { + compatible = "ti,cdce6214"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&clock_ref25m>; + clock-names = "secref"; + + clk@1 { + reg = <1>; // CDCE6214_CLK_SECREF + ti,clkin-fmt = <1>; // XTAL + }; + + clk@3 { + reg = <3>; // CDCE6214_CLK_OUT1 + ti,clkout-fmt = <0>; // CMOS + ti,cmos-mode = <1 2>; // CMOSP = highpol, CMOSN = lowpol + }; + + clk@4 { + reg = <4>; // CDCE6214_CLK_OUT2 + ti,clkout-fmt = <1>; // LVDS + }; + + clk@6 { + reg = <6>; // CDCE6214_CLK_OUT4 + ti,clkout-fmt = <2>; // LP-HCSL + }; + }; + }; diff --git a/include/dt-bindings/clock/ti,cdce6214.h b/include/dt-bindings/clock/ti,cdce6214.h new file mode 100644 index 0000000000000..1b41060896cc3 --- /dev/null +++ b/include/dt-bindings/clock/ti,cdce6214.h @@ -0,0 +1,24 @@ +#ifndef _DT_BINDINGS_CLK_TI_CDCE6214_H +#define _DT_BINDINGS_CLK_TI_CDCE6214_H + +/* + * primary/secondary inputs. Not registered as clocks, but used + * as reg properties for the subnodes specifying the input properties + */ +#define CDCE6214_CLK_PRIREF 0 +#define CDCE6214_CLK_SECREF 1 + +/* + * Clock indices for the clocks provided by the CDCE6214. Also used + * as reg properties for the subnodes specifying the output properties + */ +#define CDCE6214_CLK_OUT0 2 +#define CDCE6214_CLK_OUT1 3 +#define CDCE6214_CLK_OUT2 4 +#define CDCE6214_CLK_OUT3 5 +#define CDCE6214_CLK_OUT4 6 +#define CDCE6214_CLK_PLL 7 +#define CDCE6214_CLK_PSA 8 +#define CDCE6214_CLK_PSB 9 + +#endif /* _DT_BINDINGS_CLK_TI_CDCE6214_H */
The CDCE6214 is a Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM. This patch adds the device tree binding for this chip. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- .../devicetree/bindings/clock/ti,cdce6214.yaml | 167 +++++++++++++++++++++ include/dt-bindings/clock/ti,cdce6214.h | 24 +++ 2 files changed, 191 insertions(+)