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([82.78.167.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39d8937f0d8sm4806913f8f.40.2025.04.10.07.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 07:06:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/7] clk: renesas: rzg2l-cpg: Move pointers at the beginning of struct Date: Thu, 10 Apr 2025 17:06:23 +0300 Message-ID: <20250410140628.4124896-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250410140628.4124896-1-claudiu.beznea.uj@bp.renesas.com> References: <20250410140628.4124896-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Move pointers at the beginning of structure definition to avoid padding, if any. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 2ae36d94fbfa..bf2453900f36 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1183,20 +1183,20 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, /** * struct mstp_clock - MSTP gating clock * + * @priv: CPG/MSTP private data + * @sibling: pointer to the other coupled clock * @hw: handle between common and hardware-specific interfaces * @off: register offset * @bit: ON/MON bit * @enabled: soft state of the clock, if it is coupled with another clock - * @priv: CPG/MSTP private data - * @sibling: pointer to the other coupled clock */ struct mstp_clock { + struct rzg2l_cpg_priv *priv; + struct mstp_clock *sibling; struct clk_hw hw; u16 off; u8 bit; bool enabled; - struct rzg2l_cpg_priv *priv; - struct mstp_clock *sibling; }; #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)