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Sun, 13 Apr 2025 15:45:36 -0700 (PDT) From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Richard Cochran , Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Vinod Koul , Nikita Shubin Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v4 1/5] dt-bindings: soc: sophgo: Add SG2044 top syscon device Date: Mon, 14 Apr 2025 06:44:45 +0800 Message-ID: <20250413224450.67244-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250413224450.67244-1-inochiama@gmail.com> References: <20250413224450.67244-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SG2044 top syscon device provide PLL clock control and some other misc feature of the SoC. Add the compatible string for SG2044 top syscon device. Signed-off-by: Inochi Amaoto Reviewed-by: Krzysztof Kozlowski --- .../soc/sophgo/sophgo,sg2044-top-syscon.yaml | 49 +++++++++++++++++++ include/dt-bindings/clock/sophgo,sg2044-pll.h | 27 ++++++++++ 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2044-pll.h diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml new file mode 100644 index 000000000000..a82cc3cae576 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 SoC TOP system controller + +maintainers: + - Inochi Amaoto + +description: + The Sophgo SG2044 TOP system controller is a hardware block grouping + multiple small functions, such as clocks and some other internal + function. + +properties: + compatible: + items: + - const: sophgo,sg2044-top-syscon + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + See for valid clock. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@50000000 { + compatible = "sophgo,sg2044-top-syscon", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + clocks = <&osc>; + }; diff --git a/include/dt-bindings/clock/sophgo,sg2044-pll.h b/include/dt-bindings/clock/sophgo,sg2044-pll.h new file mode 100644 index 000000000000..817d45e700cc --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2044-pll.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ + +#define CLK_FPLL0 0 +#define CLK_FPLL1 1 +#define CLK_FPLL2 2 +#define CLK_DPLL0 3 +#define CLK_DPLL1 4 +#define CLK_DPLL2 5 +#define CLK_DPLL3 6 +#define CLK_DPLL4 7 +#define CLK_DPLL5 8 +#define CLK_DPLL6 9 +#define CLK_DPLL7 10 +#define CLK_MPLL0 11 +#define CLK_MPLL1 12 +#define CLK_MPLL2 13 +#define CLK_MPLL3 14 +#define CLK_MPLL4 15 +#define CLK_MPLL5 16 + +#endif /* __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ */