| Message ID | 20250414-qcs615-mm-v7-clock-controllers-v7-10-ebab8e3a96e9@quicinc.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show
Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com
[205.220.168.131])
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6EB826B2C6;
Mon, 14 Apr 2025 08:44:01 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=205.220.168.131
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1744620243; cv=none;
b=Wk2+hqmluZXG/qKuNv4KMvq3Fvj6fXrrh6ZdFFDjpy5e+L7VvpKgU7m2oNnWC3aVybesjrGitF1PtJRcmGmqqjgRHl3UIBr8Zp6CoL6xX69ywBTtC9T2eCQT+1NM96OHO+NvcgUG8OG3vxuFN3bx1qhV2I3MBeq0I1oKA7xMreY=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1744620243; c=relaxed/simple;
bh=i/3sCJn8w4/r+mNkGowMyPAYtfvKdXf1vRduovLlxNE=;
h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:
In-Reply-To:To:CC;
b=R1QbKQjWI4XFHldicnLzk+9prATcK6HNrcJr3QVfd0FNNCuZagriAz/Zw/BqHaGUriGVVNWcmVaszUyYQKMceGV0M3kri9RleGGE3MwgnB60Z6eE9awCK9HYrsRLQVDSmZZE4FUEy840O2r3K39tw6LvEM9T+T9n1X9sLhg3dUk=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com;
spf=pass smtp.mailfrom=quicinc.com;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b=NeWwzol+; arc=none smtp.client-ip=205.220.168.131
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b="NeWwzol+"
Received: from pps.filterd (m0279864.ppops.net [127.0.0.1])
by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id
53DNjeXa021538;
Mon, 14 Apr 2025 08:43:54 GMT
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=
cc:content-transfer-encoding:content-type:date:from:in-reply-to
:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=
kxgJMqppm+6M72Q9bPtiYVexcWKT52ob42MkDqN8lxA=; b=NeWwzol+AcPHQk9l
fMn/+T6S00ljTDQ5N1S85zic3N4fJe9ib5MIEsVifF/zLYjW3475dBEqeVpNH2L5
1EQ6kGRidM4cP+qMRJraiz1+21xvhGAZNesSvsJvfjdzdvkxUtk0FFBUHz9TurnT
POThPh3GLbY6/tmBoXl3tn0+BdWqJIoViSOzRflyBEcpqKh1MeEAo8/cSqiEsoPF
BrFQlTtwaXXcts6ig4ZxnO70RyzURJOJYHBBem0rBF0ztqg+ps2kEz6VL+U8bkpb
e/t6Yc5hjeSEQfHNRnaDu6chSY2t43iNDeufJy7d+uZjdfLn3Km5m8rk1aA0jZKj
MK+wbw==
Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com
[129.46.96.20])
by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45yhbpkrpa-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Mon, 14 Apr 2025 08:43:54 +0000 (GMT)
Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com
[10.47.209.196])
by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id
53E8hr9A018693
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Mon, 14 Apr 2025 08:43:53 GMT
Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by
nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.2.1544.9; Mon, 14 Apr 2025 01:43:49 -0700
From: Taniya Das <quic_tdas@quicinc.com>
Date: Mon, 14 Apr 2025 14:12:21 +0530
Subject: [PATCH v7 10/10] arm64: defconfig: Enable QCS615 clock controllers
Precedence: bulk
X-Mailing-List: linux-clk@vger.kernel.org
List-Id: <linux-clk.vger.kernel.org>
List-Subscribe: <mailto:linux-clk+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-clk+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-ID:
<20250414-qcs615-mm-v7-clock-controllers-v7-10-ebab8e3a96e9@quicinc.com>
References:
<20250414-qcs615-mm-v7-clock-controllers-v7-0-ebab8e3a96e9@quicinc.com>
In-Reply-To:
<20250414-qcs615-mm-v7-clock-controllers-v7-0-ebab8e3a96e9@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette
<mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring
<robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley
<conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon
<will@kernel.org>
CC: Ajit Pandey <quic_ajipan@quicinc.com>,
Imran Shaik
<quic_imrashai@quicinc.com>,
Jagadeesh Kona <quic_jkona@quicinc.com>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Taniya Das <quic_tdas@quicinc.com>
X-Mailer: b4 0.15-dev-aa3f6
X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To
nalasex01a.na.qualcomm.com (10.47.209.196)
X-QCInternal: smtphost
X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800
signatures=585085
X-Proofpoint-ORIG-GUID: THYGcC9Jo-wOZC8mzNn7oF2vAEuWBpx7
X-Proofpoint-GUID: THYGcC9Jo-wOZC8mzNn7oF2vAEuWBpx7
X-Authority-Analysis: v=2.4 cv=I+plRMgg c=1 sm=1 tr=0 ts=67fccaca cx=c_pps
a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17
a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8
a=AElZlkIX1ip-SmTVEvQA:9 a=QEXdDO2ut3YA:10
a=TjNXssC_j7lpFel5tvFf:22
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34
definitions=2025-04-14_02,2025-04-10_01,2024-11-22_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0
suspectscore=0 spamscore=0
phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0
bulkscore=0 mlxlogscore=743 clxscore=1015 impostorscore=0 malwarescore=0
classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0
reason=mlx scancount=1 engine=8.19.0-2502280000
definitions=main-2504140062
|
| Series |
Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform
|
expand
|
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c85e5da152f2a9f24fd121fca427afe428438a7..a992c4ee363a1443dfc0c5c86de2af6c0e1963f0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1355,11 +1355,15 @@ CONFIG_MSM_GCC_8998=y CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m +CONFIG_QCS_DISPCC_615=m +CONFIG_QCS_CAMCC_615=m CONFIG_QCS_GCC_404=y CONFIG_QCS_GCC_615=y CONFIG_QCS_GCC_8300=y CONFIG_SC_CAMCC_7280=m CONFIG_SA_CAMCC_8775P=m +CONFIG_QCS_GPUCC_615=m +CONFIG_QCS_VIDEOCC_615=m CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m
Enable the QCS615 display, video, camera and graphics clock controller for their respective functionalities on the Qualcomm QCS615 ride platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+)