From patchwork Wed May 30 08:43:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 10437899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 65B97602CC for ; Wed, 30 May 2018 08:43:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5455B27D0C for ; Wed, 30 May 2018 08:43:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4942A288C3; Wed, 30 May 2018 08:43:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7F6627D0C for ; Wed, 30 May 2018 08:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968778AbeE3Ind (ORCPT ); Wed, 30 May 2018 04:43:33 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:46932 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968736AbeE3In2 (ORCPT ); Wed, 30 May 2018 04:43:28 -0400 Received: by mail-lf0-f67.google.com with SMTP id h9-v6so3000773lfc.13; Wed, 30 May 2018 01:43:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=sGImT/FDh8OMYLK4F/qvz4ZUg0DtGkH24GvbZh+f+Fs=; b=HpjjqcYBU+tAft530cVmwL5BnhU2pSaEHrDm0zXMvrTbsSUY2s5ikxc4m60dMLUQfU iBB0TZiREcj5g0Hl4/58veFHOM4kFAgAWF5nZrSMe9hVXfP4eNNWlBpCeNR1RwUj6YH8 IOkbhNUoDu/OP5RVdeAJhL4t1MaHiXDUN2SO/AzGMhh/cGbU7YyaG0XbWwVxgCTcAhqN iEwX/EfvetWGzlB0CL6sjeE6+MUbYB/Y7edGUeNcZbniNoE3WS2Ir3mUjUlNyfXNAF+i MsLJBA8r+9gzl0UDSKhc9LJXCzeODl8UfwvJByhjjMoUvVVbcteD8iqJuUUUfV/TwFWV fR+w== X-Gm-Message-State: ALKqPweYP62ArVj+ol+bAgcU03/+arPRZrPb4b46mQgOldtrQeo/TyQ5 m/X3hl6kZKPlf+B/4sR++pQ= X-Google-Smtp-Source: ADUXVKKI6lzHa41xfNxuNt8jxjnRb91edvqPn/VG2tWzgIe9lXxOb5h+LDWkr1ASbxP/HT/fDc/IXg== X-Received: by 2002:a2e:1055:: with SMTP id j82-v6mr1457212lje.94.1527669806047; Wed, 30 May 2018 01:43:26 -0700 (PDT) Received: from localhost.localdomain ([213.255.186.34]) by smtp.gmail.com with ESMTPSA id g2-v6sm6920451ljj.82.2018.05.30.01.43.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 May 2018 01:43:25 -0700 (PDT) Date: Wed, 30 May 2018 11:43:19 +0300 From: Matti Vaittinen To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, lee.jones@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, mazziesaccount@gmail.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mikko.mutanen@fi.rohmeurope.com, heikki.haikola@fi.rohmeurope.com Subject: [PATCH v4 5/6] clk: bd71837: Add driver for BD71837 PMIC clock Message-ID: <3d9d7239331c30826a237ae55db28d918155d504.1527669443.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support BD71837 gateable 32768 Hz clock. Signed-off-by: Matti Vaittinen --- drivers/clk/Kconfig | 9 +++ drivers/clk/Makefile | 1 + drivers/clk/clk-bd71837.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/clk/clk-bd71837.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 41492e980ef4..4b045699bb5e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -279,6 +279,15 @@ config COMMON_CLK_STM32H7 ---help--- Support for stm32h7 SoC family clocks +config COMMON_CLK_BD71837 + tristate "Clock driver for ROHM BD71837 PMIC MFD" + depends on MFD_BD71837 + depends on I2C=y + depends on OF + help + This driver supports ROHM BD71837 PMIC clock. + + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index de6d06ac790b..8393c4af7d5a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ endif obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o +obj-$(CONFIG_COMMON_CLK_BD71837) += clk-bd71837.o obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o diff --git a/drivers/clk/clk-bd71837.c b/drivers/clk/clk-bd71837.c new file mode 100644 index 000000000000..91456d1077ac --- /dev/null +++ b/drivers/clk/clk-bd71837.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 ROHM Semiconductors +// bd71837.c -- ROHM BD71837MWV clock driver + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int bd71837_clk_enable(struct clk_hw *hw); +static void bd71837_clk_disable(struct clk_hw *hw); +static int bd71837_clk_is_enabled(struct clk_hw *hw); + +struct bd71837_clk { + struct clk_hw hw; + uint8_t reg; + uint8_t mask; + unsigned long rate; + struct platform_device *pdev; + struct bd71837 *mfd; +}; + +static unsigned long bd71837_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate); + +static const struct clk_ops bd71837_clk_ops = { + .recalc_rate = &bd71837_clk_recalc_rate, + .prepare = &bd71837_clk_enable, + .unprepare = &bd71837_clk_disable, + .is_prepared = &bd71837_clk_is_enabled, +}; + +static int bd71837_clk_set(struct clk_hw *hw, int status) +{ + struct bd71837_clk *c = container_of(hw, struct bd71837_clk, hw); + + return bd71837_update_bits(c->mfd, c->reg, c->mask, status); +} + +static void bd71837_clk_disable(struct clk_hw *hw) +{ + int rv; + struct bd71837_clk *c = container_of(hw, struct bd71837_clk, hw); + + rv = bd71837_clk_set(hw, 0); + if (rv) + dev_err(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv); +} + +static int bd71837_clk_enable(struct clk_hw *hw) +{ + return bd71837_clk_set(hw, 1); +} + +static int bd71837_clk_is_enabled(struct clk_hw *hw) +{ + struct bd71837_clk *c = container_of(hw, struct bd71837_clk, hw); + + return c->mask & bd71837_reg_read(c->mfd, c->reg); +} + +static unsigned long bd71837_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct bd71837_clk *c = container_of(hw, struct bd71837_clk, hw); + + return c->rate; +} + +static int bd71837_clk_probe(struct platform_device *pdev) +{ + struct bd71837_clk *c; + int rval = -ENOMEM; + struct bd71837 *mfd = dev_get_drvdata(pdev->dev.parent); + const char *errstr = "memory allocation for bd71837 data failed"; + struct clk_init_data init = { + .name = "bd71837-32k-out", + .ops = &bd71837_clk_ops, + }; + + c = kzalloc(sizeof(struct bd71837_clk), GFP_KERNEL); + if (!c) + goto err_out; + + c->reg = BD71837_REG_OUT32K; + c->mask = BD71837_OUT32K_EN; + c->rate = BD71837_CLK_RATE; + c->mfd = mfd; + c->pdev = pdev; + + if (pdev->dev.of_node) + of_property_read_string_index(pdev->dev.of_node, + "clock-output-names", 0, + &init.name); + + c->hw.init = &init; + + errstr = "failed to register 32K clk"; + rval = clk_hw_register(&pdev->dev, &c->hw); + if (rval) + goto err_free; + + errstr = "failed to register clkdev for bd71837"; + rval = clk_hw_register_clkdev(&c->hw, init.name, NULL); + if (rval) + goto err_unregister; + + platform_set_drvdata(pdev, c); + dev_dbg(&pdev->dev, "bd71837_clk successfully probed\n"); + + return 0; + +err_unregister: + clk_hw_unregister(&c->hw); +err_free: + kfree(c); +err_out: + dev_err(&pdev->dev, "%s\n", errstr); + return rval; +} + +static int bd71837_clk_remove(struct platform_device *pdev) +{ + struct bd71837_clk *c = platform_get_drvdata(pdev); + + if (c) { + clk_hw_unregister(&c->hw); + kfree(c); + platform_set_drvdata(pdev, NULL); + } + return 0; +} + +static struct platform_driver bd71837_clk = { + .driver = { + .name = "bd71837-clk", + }, + .probe = bd71837_clk_probe, + .remove = bd71837_clk_remove, +}; + +module_platform_driver(bd71837_clk); + +MODULE_AUTHOR("Matti Vaittinen "); +MODULE_DESCRIPTION("BD71837 chip clk driver"); +MODULE_LICENSE("GPL");