From patchwork Mon Nov 27 15:41:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 10077111 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5F18C602BC for ; Mon, 27 Nov 2017 15:44:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5061328BA7 for ; Mon, 27 Nov 2017 15:44:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 447D228C17; Mon, 27 Nov 2017 15:44:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B593D28BB5 for ; Mon, 27 Nov 2017 15:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753136AbdK0PoN (ORCPT ); Mon, 27 Nov 2017 10:44:13 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:32967 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752835AbdK0PmB (ORCPT ); Mon, 27 Nov 2017 10:42:01 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id D9E7C213DE; Mon, 27 Nov 2017 16:41:59 +0100 (CET) Received: from localhost (unknown [185.94.189.187]) by mail.free-electrons.com (Postfix) with ESMTPSA id A3862213DA; Mon, 27 Nov 2017 16:41:59 +0100 (CET) From: Maxime Ripard To: Daniel Vetter , David Airlie , Chen-Yu Tsai , Maxime Ripard Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, plaes@plaes.org, icenowy@aosc.io, Thomas Petazzoni , jernej.skrabec@siol.net Subject: [PATCH v2 01/18] dt-bindings: panel: lvds: Document power-supply property Date: Mon, 27 Nov 2017 16:41:25 +0100 Message-Id: <583a46dd967456aac07fb29529f74d91a10bdfeb.1511797218.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The power-supply property is used by a vast majority of panels, including panel-simple. Let's document it as a common property Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++++++ Documentation/devicetree/bindings/display/panel/panel-lvds.txt | 1 + 2 files changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-common.txt b/Documentation/devicetree/bindings/display/panel/panel-common.txt index ec52c472c845..125ea68052af 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-common.txt +++ b/Documentation/devicetree/bindings/display/panel/panel-common.txt @@ -78,6 +78,12 @@ used for panels that implement compatible control signals. while active. Active high reset signals can be supported by inverting the GPIO specifier polarity flag. +Power +----- + +- power-supply: many display panels need an additional power supply in + order to be fully powered-up. For such panels, power-supply contains + a phandle to the regulator powering the panel. Backlight --------- diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.txt b/Documentation/devicetree/bindings/display/panel/panel-lvds.txt index b938269f841e..250850a2150b 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.txt +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.txt @@ -32,6 +32,7 @@ Optional properties: - label: See panel-common.txt. - gpios: See panel-common.txt. - backlight: See panel-common.txt. +- power-supply: See panel-common.txt. - data-mirror: If set, reverse the bit order described in the data mappings below on all data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.