| Message ID | 778a2ce4e538bcc95a79841ddbd9713d5fc99b46.1720616233.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: rcar-gen4: Fractional PLL improvements | expand |
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index 77a4bb3e17f34848..72c740f18ac9b370 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -53,10 +53,6 @@ static u32 cpg_mode __initdata; #define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */ #define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */ -#define SSMODE_FM BIT(2) /* Fractional Multiplication */ -#define SSMODE_DITHER BIT(1) /* Frequency Dithering */ -#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ - /* PLL Clocks */ struct cpg_pll_clk { struct clk_hw hw;
All SSMODE operations are done using CPG_PLLxCR0_SSMODE*. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/clk/renesas/rcar-gen4-cpg.c | 4 ---- 1 file changed, 4 deletions(-)