From patchwork Tue Feb 14 17:01:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9572283 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 29A9E60578 for ; Tue, 14 Feb 2017 17:03:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A764205AF for ; Tue, 14 Feb 2017 17:03:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F34F228433; Tue, 14 Feb 2017 17:03:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 468D8205AF for ; Tue, 14 Feb 2017 17:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932168AbdBNRCT (ORCPT ); Tue, 14 Feb 2017 12:02:19 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:52356 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753129AbdBNRCO (ORCPT ); Tue, 14 Feb 2017 12:02:14 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 6087E20B95; Tue, 14 Feb 2017 18:02:11 +0100 (CET) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id 29A162055D; Tue, 14 Feb 2017 18:02:01 +0100 (CET) From: Gregory CLEMENT To: Ulf Hansson , Adrian Hunter , linux-mmc@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Mike Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Ziji Hu , Jimmy Xu , Jisheng Zhang , Nadav Haklai , Ryan Gao , Doug Jones , Victor Gu , "Wei(SOCP) Liu" , Wilson Ding , Yehuda Yitschak , Marcin Wojtas , Hanna Hawa , Kostya Porotchkin , Russell King Subject: [PATCH v6 01/14] clk: apn806: Add eMMC clock to system controller driver Date: Tue, 14 Feb 2017 18:01:41 +0100 Message-Id: <83800a641e82cd7dc653cd7b7728f4bb432407a2.1487091464.git-series.gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Konstantin Porotchkin Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by: Konstantin Porotchkin Reviewed-by: Omri Itach Reviewed-by: Hanna Hawa [fixed up conflicts, added error handling --rmk] Signed-off-by: Russell King Acked-by: Stephen Boyd Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++- drivers/clk/mvebu/ap806-system-controller.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index a749ba2edec4..5019c8f4acd0 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -235,7 +235,8 @@ #clock-cells = <1>; clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1", - "ap-fixed", "ap-mss"; + "ap-fixed", "ap-mss", + "ap-emmc"; reg = <0x6f4000 0x1000>; }; }; diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index 8181b919f062..0a785076b0c6 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -23,7 +23,7 @@ #define AP806_SAR_REG 0x400 #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f -#define AP806_CLK_NUM 4 +#define AP806_CLK_NUM 5 static struct clk *ap806_clks[AP806_CLK_NUM]; @@ -117,6 +117,17 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev) goto fail3; } + /* eMMC Clock is fixed clock divided by 3 */ + of_property_read_string_index(np, "clock-output-names", + 4, &name); + ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name, + 0, 1, 3); + if (IS_ERR(ap806_clks[4])) { + ret = PTR_ERR(ap806_clks[4]); + goto fail4; + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); if (ret) goto fail_clk_add; @@ -124,6 +135,8 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev) return 0; fail_clk_add: + clk_unregister_fixed_factor(ap806_clks[4]); +fail4: clk_unregister_fixed_factor(ap806_clks[3]); fail3: clk_unregister_fixed_rate(ap806_clks[2]);