From patchwork Mon Jul 22 11:50:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13738779 Received: from riemann.telenet-ops.be (riemann.telenet-ops.be [195.130.137.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED45161339 for ; Mon, 22 Jul 2024 11:59:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721649561; cv=none; b=jmnww1aC2iBdg7VK2PcIiHOr9Jlj/njfckJwjraaDB3w/TzumKlyZS8pF0CCG9vzYqYUWespfp3sG7tFy52CRKk/tD9w5ZsuYkCF3RkPz4IEGJnyaDWAsohw9EoqFzKKtKeydFH5bwYloUEyaibL7EWDl+5PFKCem4yZzG3RrdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721649561; c=relaxed/simple; bh=P/xhWjvkOurIQAUdHFphv+ELwI7u0tV8QHMAFEXFaH4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H0mnf/jovVA+6oVXzR/ckzZs+IS+mFMIPwJfuCYMGwcedAI1Qk2zXA718V+Bi7kPspsxjMaYgWjzR5z0hEuoeE11v+pgc3eBBTVeVOyPro3NuZyUIKHGte3x6krw1hD39i6ez7ltoYmlQ30e3QsrTU7kmPxtT77vBpCVjnGvbV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from michel.telenet-ops.be (michel.telenet-ops.be [IPv6:2a02:1800:110:4::f00:18]) by riemann.telenet-ops.be (Postfix) with ESMTPS id 4WSJWS2fglz4x1mD for ; Mon, 22 Jul 2024 13:50:44 +0200 (CEST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:173b:9414:53f5:de4c]) by michel.telenet-ops.be with bizsmtp id qbqc2C00N1wvoRx06bqcKo; Mon, 22 Jul 2024 13:50:37 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1sVrYY-002zAq-AZ; Mon, 22 Jul 2024 13:50:36 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1sVrYq-0020iC-QT; Mon, 22 Jul 2024 13:50:36 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Geert Uytterhoeven , Yoshihiro Shimoda Subject: [PATCH v2 10/15] clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs Date: Mon, 22 Jul 2024 13:50:30 +0200 Message-Id: <8544571f507e00ed6fc61617d27c9e19de5e9d11.1721648548.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and PLL6 as variable fractional PLLs. Note that the R-Car Gen4 clock driver does not support variable 9.24 PLLs yet, so the driver will downgrade them to fixed fractional PLLs, too. Reformat nearby lines to retain a consistent layout. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 832ba0bacdf02346..b6b6012f71238627 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -57,12 +57,12 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), - DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), - DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), - DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_GEN4_PLL_F9_24(".pll1", 1, CLK_PLL1, CLK_MAIN), + DEF_GEN4_PLL_V9_24(".pll2", 2, CLK_PLL2, CLK_MAIN), + DEF_GEN4_PLL_V9_24(".pll3", 3, CLK_PLL3, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_GEN4_PLL_V9_24(".pll6", 6, CLK_PLL6, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),