| Message ID | 8dfe0935d35b8a218ebf39d37113e27289a0de9b.1475571575.git.mylene.josserand@free-electrons.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
Hello,
On Tue, 4 Oct 2016 11:46:15 +0200, Mylène Josserand wrote:
> Add the flag CLK_SET_RATE_PARENT to 'ac-dig' clock.
There is no need to repeat the commit title inside the commit log
itself. What would be more useful is to explain *why* this is needed.
Thomas
Hello Thomas, On 04/10/2016 14:12, Thomas Petazzoni wrote: > Hello, > > On Tue, 4 Oct 2016 11:46:15 +0200, Mylène Josserand wrote: >> Add the flag CLK_SET_RATE_PARENT to 'ac-dig' clock. > > There is no need to repeat the commit title inside the commit log > itself. What would be more useful is to explain *why* this is needed. Agreed, I will update it for a V2. Thanks !
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 96b40ca..37c4d8d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -440,7 +440,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", - 0x140, BIT(31), 0); + 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 0x140, BIT(30), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
Add the flag CLK_SET_RATE_PARENT to 'ac-dig' clock. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)