From patchwork Fri Nov 1 03:19:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 13858673 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 065D313C9A4; Fri, 1 Nov 2024 03:20:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730431206; cv=none; b=lKVkc/Ynm9+V12wEn6QdMhKToeG3cS0cZmrVCFzoFtk/NvsytLt2tJemffM1RkNsL49rmFFA/L3QIXw4tf7JcvlEAxOnWDQPB3MDIK3Kk89nA1Z4Q9/RyCOL5P4/ZkDdz9fQMQr3rldLx5q1MzB1GUkrDR1lTThjZGsEXRRiHSA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730431206; c=relaxed/simple; bh=vijiu73JL6D+88+Bhdsv/dQtGF+EY3iYKq6k3StPqyM=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=glnK2I0el3bSNk5sKa6uGejXWx95JMOzTzyLA7D2YfmN22sQfSfKC84gnTmJJoXMFehRFjEWf7Njvuj7d1NhXmgOqY9bL/HDT3OoHzu9Q2S0ZkivW97n5TailvZiEy7tozE1hSGG1mA+k63QoXa+V5DerRGB2VZ+wSlIfkd4IOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98) (envelope-from ) id 1t6iCU-00000000478-2NIb; Fri, 01 Nov 2024 03:19:50 +0000 Date: Fri, 1 Nov 2024 03:19:39 +0000 From: Daniel Golle To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe =?iso-8859-1?q?Kleine-K=F6nig?= , Sam Shih , Frank Wunderlich , Daniel Golle , AngeloGioacchino Del Regno , Matthias Brugger , Stephen Boyd , Michael Turquette Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical Message-ID: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline SPI0 clocks have wrongly been marked as critical while, probably due to the SPI driver not requesting them. This can (and should) be addressed in device tree instead. Remove CLK_IS_CRITICAL flag from clocks related to SPI0. Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC") Signed-off-by: Daniel Golle --- drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c index ef8267319d91..c40e18c27f12 100644 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, CLK_IS_CRITICAL), - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, - CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12), GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, - CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15), GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),