| Message ID | aaad6e257a44e312cfbeb5a8ce84b8975cdc461e.1708223519.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | riscv: sophgo: add clock support for sg2042 | expand |
On Sun, Feb 18, 2024 at 10:51 AM Chen Wang <unicornxw@gmail.com> wrote: > > From: Chen Wang <unicorn_wang@outlook.com> > > Add bindings for the pll clocks for Sophgo SG2042. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++ > include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++ > 2 files changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml > create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h > > diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml > new file mode 100644 > index 000000000000..b9af733e8a73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 PLL Clock Generator > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +properties: > + compatible: > + const: sophgo,sg2042-pll > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) > + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) > + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) > + > + '#clock-cells': > + const: 1 > + description: > + See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices. > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@10000000 { > + compatible = "sophgo,sg2042-pll"; > + reg = <0x10000000 0x10000>; > + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h > new file mode 100644 > index 000000000000..2d519b3bf51c > --- /dev/null > +++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ > +/* > + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. > + */ > + > +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ > +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ > + > +#define MPLL_CLK 0 > +#define FPLL_CLK 1 > +#define DPLL0_CLK 2 > +#define DPLL1_CLK 3 > + > +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */ > -- > 2.25.1 > Reviewed-by: Guo Ren <guoren@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file mode 100644 index 000000000000..b9af733e8a73 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PLL Clock Generator + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +properties: + compatible: + const: sophgo,sg2042-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-pll"; + reg = <0x10000000 0x10000>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h new file mode 100644 index 000000000000..2d519b3bf51c --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */