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AJvYcCU2cIsGjGagN89hTR7rIMeY80FuDRz6YZi/J1DuMMgJu/3eXtUdll7f931pOaICcCyS3M38GPUJzzEPfBPoNz8cXkPhTLurcNkQS6ByDEOfgBKZDbS8rMupEowLkpYkZ7fPd31LozDpoY9wNoSfg4B2BiKE0DMGGpFvS1SI9Fno/ajdwQ== X-Gm-Message-State: AOJu0Ywn0Sn56Nhpe5uIWDGjoA3eX8QfAH7fz4gJe+6g+Dd36KL3ULwU EWpuaRrqjP4k2NYy6Qx/LEAYgYHywcv38uCuAxIEZaUK9MGW4erH X-Google-Smtp-Source: AGHT+IEiYNzDXEQXqHIf5Bob3BZZiHADsLv+HRhoLak/eB89MmVLfHVQYczKxLEVNI0n4ewD2zaOUA== X-Received: by 2002:a4a:241d:0:b0:59f:91de:26c8 with SMTP id m29-20020a4a241d000000b0059f91de26c8mr7420030oof.5.1708224664382; Sat, 17 Feb 2024 18:51:04 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id br21-20020a0568201a5500b0059fae4c8100sm510680oob.0.2024.02.17.18.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Feb 2024 18:51:04 -0800 (PST) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang , Rob Herring Subject: [PATCH v10 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042 Date: Sun, 18 Feb 2024 10:50:56 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add bindings for the pll clocks for Sophgo SG2042. Signed-off-by: Chen Wang Reviewed-by: Rob Herring Reviewed-by: Guo Ren --- .../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++ 2 files changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file mode 100644 index 000000000000..b9af733e8a73 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PLL Clock Generator + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-pll"; + reg = <0x10000000 0x10000>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h new file mode 100644 index 000000000000..2d519b3bf51c --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */