From patchwork Tue Mar 7 08:56:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9608417 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED34B60414 for ; Tue, 7 Mar 2017 09:30:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAAF825D9E for ; Tue, 7 Mar 2017 09:30:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF27A284A5; Tue, 7 Mar 2017 09:30:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8407625D9E for ; Tue, 7 Mar 2017 09:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755318AbdCGJa0 (ORCPT ); Tue, 7 Mar 2017 04:30:26 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:50852 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755012AbdCGJ32 (ORCPT ); Tue, 7 Mar 2017 04:29:28 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 790F120BC3; Tue, 7 Mar 2017 09:56:56 +0100 (CET) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id C8542207CF; Tue, 7 Mar 2017 09:56:37 +0100 (CET) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , Chen-Yu Tsai , Maxime Ripard Cc: dri-devel@lists.freedesktop.org, Daniel Vetter , David Airlie , Mark Rutland , Rob Herring , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 6/15] dt-bindings: display: sun4i: Add HDMI display bindings Date: Tue, 7 Mar 2017 09:56:25 +0100 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP One of the possible output of the display pipeline, on the SoCs that have it, is the HDMI controller. Add a binding for it. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 21 +++++++- 1 file changed, 21 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index b82c00449468..4b280672658e 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -4,6 +4,27 @@ Allwinner A10 Display Pipeline The Allwinner A10 Display pipeline is composed of several components that are going to be documented below: +HDMI Encoder +------------ + +The HDMI Encoder supports the HDMI video and audio outputs, and does +CEC. It is one end of the pipeline. + +Required properties: + - compatible: value must be one of: + * allwinner,sun5i-a10s-hdmi + - reg: base address and size of memory-mapped region + - clocks: phandles to the clocks feeding the HDMI encoder + * ahb: the HDMI interface clock + * mod: the HDMI module clock + * pll-0: the first video PLL + * pll-1: the second video PLL + - clock-names: the clock names mentioned above + + - ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint. + TV Encoder ----------