From patchwork Fri Jun 28 07:39:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leonard Crestez X-Patchwork-Id: 11021555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A94EA299D for ; Fri, 28 Jun 2019 07:40:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 975C32849B for ; Fri, 28 Jun 2019 07:40:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86D59287A5; Fri, 28 Jun 2019 07:40:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10D9D287A1 for ; Fri, 28 Jun 2019 07:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726616AbfF1HkK (ORCPT ); Fri, 28 Jun 2019 03:40:10 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55130 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbfF1HkJ (ORCPT ); Fri, 28 Jun 2019 03:40:09 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id AA7961A0DC4; Fri, 28 Jun 2019 09:40:08 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9D9231A0346; Fri, 28 Jun 2019 09:40:08 +0200 (CEST) Received: from fsr-ub1864-112.ea.freescale.net (fsr-ub1864-112.ea.freescale.net [10.171.82.98]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id B4496205D5; Fri, 28 Jun 2019 09:40:07 +0200 (CEST) From: Leonard Crestez To: Alexandre Bailon , Georgi Djakov , Stephen Boyd , Michael Turquette , Viresh Kumar Cc: MyungJoo Ham , Kyungmin Park , Shawn Guo , Dong Aisheng , Fabio Estevam , "Rafael J. Wysocki" , Jacky Bai , Anson Huang , Abel Vesa , Krzysztof Kozlowski , Ulf Hansson , Saravana Kannan , kernel@pengutronix.de, linux-imx@nxp.com, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFCv2 8/8] arm64: dts: imx8mm: Add devfreq-imx nodes Date: Fri, 28 Jun 2019 10:39:56 +0300 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The imx8mm has multiple buses which can be scaled with some degree of independence. Expose them as devfreq devices for userspace scaling. It shouldn't be possible to get the system in a non-working state this way. It is primarily aimed at testing and fine performance tuning. Signed-off-by: Leonard Crestez --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 3b4b112814f7..aa9ed418652d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -121,10 +121,32 @@ opp-supported-hw = <0x8>, <0x7>; clock-latency-ns = <150000>; }; }; + ddrc_opp_table: ddrc-opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; + + noc_opp_table: noc-opp-table { + compatible = "operating-points-v2"; + + opp-150M { + opp-hz = /bits/ 64 <150000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x80000000>; }; @@ -748,10 +770,35 @@ status = "disabled"; }; }; + pl301_main: nic@32000000 { + compatible = "fsl,imx8mm-nic"; + reg = <0x32000000 0x100000>; + clocks = <&clk IMX8MM_CLK_MAIN_AXI>; + }; + + pl301_wakeup: nic@32100000 { + compatible = "fsl,imx8mm-nic"; + reg = <0x32100000 0x100000>; + clocks = <&clk IMX8MM_CLK_AHB>; + }; + + pl301_enet: nic@32400000 { + compatible = "fsl,imx8mm-nic"; + reg = <0x32400000 0x100000>; + clocks = <&clk IMX8MM_CLK_ENET_AXI>; + }; + + noc: noc@32700000 { + compatible = "fsl,imx8mm-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + operating-points-v2 = <&noc_opp_table>; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -835,7 +882,14 @@ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; interrupts = ; }; + + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc"; + reg = <0x3d400000 0x400000>; + clocks = <&clk IMX8MM_CLK_DRAM>; + operating-points-v2 = <&ddrc_opp_table>; + }; }; };