diff mbox series

clk: renesas: r8a779g0: Fix PCIe clock name

Message ID f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: renesas: r8a779g0: Fix PCIe clock name | expand

Commit Message

Geert Uytterhoeven Jan. 30, 2024, 9:47 a.m. UTC
Fix a typo in the name of the module clock for the second PCIe channel.

Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-clk for v6.9.

 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Wolfram Sang Jan. 30, 2024, 9:53 a.m. UTC | #1
On Tue, Jan 30, 2024 at 10:47:49AM +0100, Geert Uytterhoeven wrote:
> Fix a typo in the name of the module clock for the second PCIe channel.
> 
> Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 0acc301221e552f7..c4b1938db76b35f4 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -194,7 +194,7 @@  static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 	DEF_MOD("msi4",		622,	R8A779G0_CLK_MSO),
 	DEF_MOD("msi5",		623,	R8A779G0_CLK_MSO),
 	DEF_MOD("pciec0",	624,	R8A779G0_CLK_S0D2_HSC),
-	DEF_MOD("pscie1",	625,	R8A779G0_CLK_S0D2_HSC),
+	DEF_MOD("pciec1",	625,	R8A779G0_CLK_S0D2_HSC),
 	DEF_MOD("pwm",		628,	R8A779G0_CLK_SASYNCPERD4),
 	DEF_MOD("rpc-if",	629,	R8A779G0_CLK_RPCD2),
 	DEF_MOD("scif0",	702,	R8A779G0_CLK_SASYNCPERD4),