From patchwork Mon Dec 4 12:56:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13478324 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="f7+hcN9Z" Received: from mail-oa1-x2f.google.com (mail-oa1-x2f.google.com [IPv6:2001:4860:4864:20::2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5E7810E; Mon, 4 Dec 2023 04:57:07 -0800 (PST) Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1faf56466baso2336051fac.3; Mon, 04 Dec 2023 04:57:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701694627; x=1702299427; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x7obvGCBMmltBjy5XbnnE2I2O+AT6oEkcBU325Ni1XM=; b=f7+hcN9Z173XZusF6WIUkhRdkrGluTzsLmE1ukAsfO+iHpv6UwNmzK+4In/VIAq+w5 gzwn4pwlyPxa7R3Zzcf+TM9DDxsXQ8uPSCaUgw/hKWeuut8PEvBiDVJK5UCnPlEx6opj tcCIGSc0q9dLc7cm0HppeY83lEa/X+zkuICZj/RacuZ71UnW3BpoVLcfHc6Ohj3Z/iwN dkbfSpAC9966cbpA2rEQVfTBlu6zxpHH9V4B3mKl9rHJLM98nHbyb5r90gz62ylhOPX9 HWGSAj15SwINo5Q6Sr++x3iHdzfNcJ74CJ9m+nlB3h1Imtf2Mutbj1OBeXSsMlAL5+YO sZig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701694627; x=1702299427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x7obvGCBMmltBjy5XbnnE2I2O+AT6oEkcBU325Ni1XM=; b=jK92zJd/D4h81Qt9ld4m4H89Lh8OFTziBqu3kLIqpkUs+rmQqpe7d1NPzj9rg3q93b 7P1F8Mh5BCrbwXQfu0iBd3+08o8EJeEygFQ+aI9gVw4+5YNp9AcSQJObDrSiulpcjZbY S/0QNPwJn4NcJdsQGkhIdzgmN6dUiQU1+Rgm9y7sdUIFet/Jnzl/IWwWLypYZo2niro/ hVd/xoTDyxHTdmFvSoPypVq7LblH4Od2uiJ/0i0J3Q+iEHs9AaRpbwkhFIWhKag6x2QJ Zek5ohcEa13PF0DnAZXX1j5KfxXGeVCkJMtNbdx1lGhGamfvMRxusOQlAiyjoPeuSYeB ZMrw== X-Gm-Message-State: AOJu0YwjFxNE4Wx86XloJqnaFnwhjRIXmtqp4q/qfW9RxUfLMuavkkE1 3Rtk3NXokw8lriITDZEPt5Q= X-Google-Smtp-Source: AGHT+IFvpW5846gC1OX97+GsC+iqJkisXIF8htbICn6H5+/H37RciiMedCYdMsfPkXiayqXnoNfdvw== X-Received: by 2002:a05:6870:d613:b0:1fa:fc26:7f81 with SMTP id a19-20020a056870d61300b001fafc267f81mr5190047oaq.14.1701694626940; Mon, 04 Dec 2023 04:57:06 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id wc12-20020a056871a50c00b001fa3c734bc5sm2827332oab.46.2023.12.04.04.57.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:57:06 -0800 (PST) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang Subject: [PATCH v3 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Date: Mon, 4 Dec 2023 20:56:57 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 79 +++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 49b4b9c2c101..0b3b3b2b0c64 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -14,6 +14,10 @@ chosen { }; }; +&cgi { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 93256540d078..ecc7758073af 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "sg2042-cpus.dtsi" @@ -18,6 +19,12 @@ aliases { serial0 = &uart0; }; + cgi: oscillator { + compatible = "fixed-clock"; + clock-output-names = "cgi"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; @@ -311,12 +318,84 @@ intc: interrupt-controller@7090000000 { riscv,ndev = <224>; }; + sys_ctrl: system-controller@7030010000 { + compatible = "sophgo,sg2042-sysctrl"; + reg = <0x70 0x30010000 0x0 0x1000>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + system-ctrl = <&sys_ctrl>; + #clock-cells = <1>; + clocks = <&cgi>; + assigned-clocks = \ + <&clkgen DIV_CLK_FPLL_RP_CPU_NORMAL_1>, + <&clkgen DIV_CLK_FPLL_50M_A53>, + <&clkgen DIV_CLK_FPLL_TOP_RP_CMN_DIV2>, + <&clkgen DIV_CLK_FPLL_UART_500M>, + <&clkgen DIV_CLK_FPLL_AHB_LPC>, + <&clkgen DIV_CLK_FPLL_EFUSE>, + <&clkgen DIV_CLK_FPLL_TX_ETH0>, + <&clkgen DIV_CLK_FPLL_PTP_REF_I_ETH0>, + <&clkgen DIV_CLK_FPLL_REF_ETH0>, + <&clkgen DIV_CLK_FPLL_EMMC>, + <&clkgen DIV_CLK_FPLL_SD>, + <&clkgen DIV_CLK_FPLL_TOP_AXI0>, + <&clkgen DIV_CLK_FPLL_TOP_AXI_HSPERI>, + <&clkgen DIV_CLK_FPLL_AXI_DDR_1>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER1>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER2>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER3>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER4>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER5>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER6>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER7>, + <&clkgen DIV_CLK_FPLL_DIV_TIMER8>, + <&clkgen DIV_CLK_FPLL_100K_EMMC>, + <&clkgen DIV_CLK_FPLL_100K_SD>, + <&clkgen DIV_CLK_FPLL_GPIO_DB>, + <&clkgen DIV_CLK_MPLL_RP_CPU_NORMAL_0>, + <&clkgen DIV_CLK_MPLL_AXI_DDR_0>; + assigned-clock-rates = \ + <2000000000>, + <50000000>, + <1000000000>, + <500000000>, + <200000000>, + <25000000>, + <125000000>, + <50000000>, + <25000000>, + <100000000>, + <100000000>, + <100000000>, + <250000000>, + <1000000000>, + <50000000>, + <50000000>, + <50000000>, + <50000000>, + <50000000>, + <50000000>, + <50000000>, + <50000000>, + <100000>, + <100000>, + <100000>, + <2000000000>, + <1000000000>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";