From patchwork Thu Feb 15 14:23:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 10221379 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D038602CB for ; Thu, 15 Feb 2018 14:23:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D00828334 for ; Thu, 15 Feb 2018 14:23:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00FB72937B; Thu, 15 Feb 2018 14:23:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D153F28334 for ; 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Thu, 15 Feb 2018 14:23:09 +0000 (GMT) Received: from epcas1p4.samsung.com ( [182.195.41.48]) by epsmges1p3.samsung.com (Symantec Messaging Gateway) with SMTP id EE.99.04137.DC7958A5; Thu, 15 Feb 2018 23:23:09 +0900 (KST) Received: from epsmgms2p1new.samsung.com (unknown [182.195.42.142]) by epcas1p4.samsung.com (KnoxPortal) with ESMTP id 20180215142309epcas1p490a2620491f153ea69c7f0c4888a76a8~ThccMFcLy1669216692epcas1p4Q; Thu, 15 Feb 2018 14:23:09 +0000 (GMT) X-AuditID: b6c32a37-433ff70000001029-36-5a8597cdeb7b Received: from epmmp1.local.host ( [203.254.227.16]) by epsmgms2p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 1E.F6.03826.DC7958A5; Thu, 15 Feb 2018 23:23:09 +0900 (KST) MIME-version: 1.0 Content-type: text/plain; charset="utf-8" Received: from [106.116.147.40] by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P4700A083YG5620@mmp1.samsung.com>; Thu, 15 Feb 2018 23:23:09 +0900 (KST) Subject: Re: [PATCH 4/7] clk: samsung: exynos5433: fix PLL rates To: Chanwoo Choi , Andrzej Hajda Cc: Bartlomiej Zolnierkiewicz , Marek Szyprowski , Tomasz Figa , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , "moderated list:SAMSUNG SOC CLOCK DRIVERS" , "open list:COMMON CLK FRAMEWORK" , "Chanwoo Choi (gmail)" , =?UTF-8?B?7LWc7LCs7JqwIChzYW1zdW5nLmNvbSk=?= From: Sylwester Nawrocki Message-id: Date: Thu, 15 Feb 2018 15:23:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 In-reply-to: <5A83CD07.3060008@samsung.com> Content-language: en-GB Content-transfer-encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIKsWRmVeSWpSXmKPExsWy7bCmge7Z6a1RBuseqlvcWneO1WLjjPWs FhNvXGGxuP7lOavFs6PaFv2PXzNbnD+/gd3iY889VosZ5/cxWaw9cpfd4uIpV4t/1zayWKza 9YfRgdfj/Y1Wdo+ds+6ye2xa1cnm0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBkL1p5lK5ip UvH440u2BsaFsl2MHBwSAiYS5zZ5dzFycQgJ7GCU+DT1JzOE851R4uTnz0AOJ1jRpZvtrBCJ 3YwSizZ+ZQVJ8AoISvyYfI8FxGYW0JR48WUSC0TRfUaJxx8vMIEkhAUcJG5PawBrEBHwl+je tJkNpIhZYBWLxN+FjYwgCTYBQ4neo32MEFPtJO5+2s8GYrMIqEqsujEDLC4qECGxcOpTMJtT QFviRdcNdojN4hLH7t9khLDlJQ5eeQ52hYTAfzaJzsen2CF+cJE4uHMeK4QtLPHq+BZ2SABI S1w6agtR388o8fH4fqjm1YwSr7/tgmqwljh8/CIrxAY+iXdfe1ghmnklOtqEIEo8JKY8/MMC YTtKnJnYywQJiluMEn8f/GacwCg3CynIZiEF2SwkT8xC8sQCRpZVjGKpBcW56anFhgXGesWJ ucWleel6yfm5mxjBCUnLfAfjhnM+hxgFOBiVeHg39LZGCbEmlhVX5h5ilOBgVhLh/RgFFOJN SaysSi3Kjy8qzUktPsQozcGiJM4bEOASJSSQnliSmp2aWpBaBJNl4uCUamDUP9acK5+y/8BH nU6nCQzLSifm3zm3m895y9WbsTP46xffnz+5usrj4EzWykfr4nPvqW4Rm/L79aSO3wZrXhx5 vKnv+ZscKddbvN7BnFFZdXEzggI+XZZ4G2m2offc2f5Aw9UO+486n5VRm/Db6/+Pd5tPr6y6 LNzzXmtmkUN4a8PNvNMVPg/+KLEUZyQaajEXFScCAMo4XjFEAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42I5/e+xgO7Z6a1RBmd3c1ncWneO1WLjjPWs FhNvXGGxuP7lOavFs6PaFv2PXzNbnD+/gd3iY889VosZ5/cxWaw9cpfd4uIpV4t/1zayWKza 9YfRgdfj/Y1Wdo+ds+6ye2xa1cnm0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBkL1p5lK5ip UvH440u2BsaFsl2MnBwSAiYSl262s3YxcnEICexklFjZc5sFJMErICjxY/I9IJuDg1lAXWLK lFyQsJDAQ0aJNQudQGxhAQeJ29MaWEFsEQFfiTWHZjODzGEWWMci0fz6GAvE0FuMElO73rKD VLEJGEr0Hu1jhFhgJ3H30342EJtFQFVi1Y0ZYHFRgQiJzpXzwY7gFNCWeNF1A6yXWUBc4tj9 m4wQtrzEwSvPWSYwCsxCcusshFtnIemYhaRjASPLKkbJ1ILi3PTcYqMCw7zUcr3ixNzi0rx0 veT83E2MwOjZdlirbwfj/SXxhxgFOBiVeHg39LZGCbEmlhVX5h5ilOBgVhLh/RgFFOJNSays Si3Kjy8qzUktPsQozcGiJM57O+9YpJBAemJJanZqakFqEUyWiYNTqoFxeQbP7vdTXd2u+z0/ stcub+/tmplXJh7gEma0y/43o2mnK39e03QudYllWQl6y3LWXNjOUZl1dMK1eR++fI4t3WGy vdgl9h23xS6eT4I21jvP/js0ge1I5XTfjV9OnLB2XnZOZufd6iMn7G6tllBPC1N/JqKU9ehv SjlPv0O3c2+OrS//+9O/lViKMxINtZiLihMBir76e5oCAAA= X-CMS-MailID: 20180215142309epcas1p490a2620491f153ea69c7f0c4888a76a8 X-Msg-Generator: CA CMS-TYPE: 101P X-CMS-RootMailID: 20180213134101eucas1p1f9348abc0344594476bc8618c1006e31 X-RootMTR: 20180213134101eucas1p1f9348abc0344594476bc8618c1006e31 References: <20180213134032.30235-1-a.hajda@samsung.com> <20180213134032.30235-5-a.hajda@samsung.com> <5A83CD07.3060008@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Chanwoo, On 02/14/2018 06:45 AM, Chanwoo Choi wrote: > Exynos5433 TRM shows different PLL frequency from the calculated value. > Actually, I'm not sure which value is the correct value between TRM's> value and real calculated value. > > If we only consider the equation, I agree that we have to replace them > with real calculated value with equation. But, TRM shows the diagram of > clock domain which contains the multiple IPs. And each diagram specifies > the required source clock rate of each child IP. Maybe, this source clock > rate might be calculated from the PLL rate provided by TRM. (even if it's > different from real calculated value). > > Although the real rate is a little bit incorrect, we might better to keep > PLL rate provided by TRM in order to get the required source clock of child > IPs as the TRM. If we modify the PLL rate provided by TRM, the source clock > rate of child IP might be different from TRM. > > Basically, I have no objection of this patch. Just I think that need to > check it. In order to have the clk API behave properly we need to have in these tables frequency values matching the values returned by the recalc_rate callback for given P, M, S, K coefficients. Alternatively, we could decrease precision of the PLL's recalc_rate() callbacks by rounding its return value, but I'm not sure it's a good approach. It might be better to have clear indication which P, M, S, K values yield higher frequency error, even though the differences at those least significant digit positions might be meaningless, considering frequency tolerance of the root oscillator itself. For example, difference of 10 Hz where Fout = 400 MHz is only 0.025 ppm (0.0000025 %), when the tolerance of the root oscillator itself will be usually in range 10...100 ppm. In the TRMs the least significant digits are simply ignored AFAIU. I guess we could apply similar rounding in the recalc_rate callback of the fractional PLLs and the problem would also be solved, e.g. I think we need a bit more detailed commit message for this patch series, so it's clear what are the issues with current values. > On 2018년 02월 13일 22:40, Andrzej Hajda wrote: >> Declared rates did not match rates generated by PLL. >> As a result driver behaved inconsitently. >> >> Signed-off-by: Andrzej Hajda >> --- >> drivers/clk/samsung/clk-exynos5433.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c >> index db270908037a..335bebfa21c0 100644 >> --- a/drivers/clk/samsung/clk-exynos5433.c >> +++ b/drivers/clk/samsung/clk-exynos5433.c >> @@ -729,7 +729,7 @@ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = >> PLL_35XX_RATE(800000000U, 400, 6, 1), >> PLL_35XX_RATE(733000000U, 733, 12, 1), >> PLL_35XX_RATE(700000000U, 175, 3, 1), >> - PLL_35XX_RATE(667000000U, 222, 4, 1), >> + PLL_35XX_RATE(666000000U, 222, 4, 1), >> PLL_35XX_RATE(633000000U, 211, 4, 1), >> PLL_35XX_RATE(600000000U, 500, 5, 2), >> PLL_35XX_RATE(552000000U, 460, 5, 2), >> @@ -757,12 +757,12 @@ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = >> /* AUD_PLL */ >> static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { >> PLL_36XX_RATE(400000000U, 200, 3, 2, 0), >> - PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), >> + PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), >> PLL_36XX_RATE(384000000U, 128, 2, 2, 0), >> - PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), >> - PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), >> - PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), >> - PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), >> + PLL_36XX_RATE(368639991U, 246, 4, 2, -15729), >> + PLL_36XX_RATE(361507202U, 181, 3, 2, -16148), >> + PLL_36XX_RATE(338687988U, 113, 2, 2, -6816), >> + PLL_36XX_RATE(294912002U, 98, 1, 3, 19923), >> PLL_36XX_RATE(288000000U, 96, 1, 3, 0), >> PLL_36XX_RATE(252000000U, 84, 1, 3, 0), >> { /* sentinel */ } --- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 1c4c7a3039f1..d7a265827e65 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -300,6 +300,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, do_div(fvco, (pdiv << sdiv)); fvco >>= 16; + fvco = ((fvco + 50) / 100) * 100; + return (unsigned long)fvco; }