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Fri, 17 Jul 2015 13:56:29 +0000 Received: from enigma.ea.freescale.net (enigma.ea.freescale.net [10.171.77.120]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6HDuOo0027168; Fri, 17 Jul 2015 06:56:28 -0700 From: =?UTF-8?q?Horia=20Geant=C4=83?= To: Herbert Xu CC: Subject: [PATCH 2/4] crypto: caam - fix snooping for write transactions Date: Fri, 17 Jul 2015 16:54:52 +0300 Message-ID: <1437141294-15678-2-git-send-email-horia.geanta@freescale.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1437141294-15678-1-git-send-email-horia.geanta@freescale.com> References: <1437141294-15678-1-git-send-email-horia.geanta@freescale.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD009; 1:Ijgkmk1p+W52jHoUphLt1qjrBWWWQNRAeYAg9mAK70WtXMc6RVkM5uPtW4EZ4lUrW+p9i4qii85M11f5GnHXv7gMqiqphFlrN4pBimzWQO48TVXxJwNV8I4XessIfR+8ev837UxmuE88rewjOm8NvUfWrPc7wZEcvquPtIFcqr7ViRsrb0St+7snPYfCNid+dCWeEnwKkVgqjoQ0nNcDQyPaLkYbN5YdXNS8x9d/HNeSGndzB2Pdzf+hFXeXMygJxRNZL6BbWRWaip07z3ktpJ47Og2L7d9G8fquvXuLgFUeGSkObw+3/oPYXjyqNRIIAxds1E203mbhjLgnA6Zl+fWDJ57FOy0tVVw31tB8fjSAVHWqCxeMX+VNSNukgpb7nk2iuOfHywQL/fk/YM3a0a1T6F10WrBMyWGu+zexUSk= X-Forefront-Antispam-Report: CIP:192.88.168.50; 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It has to be programmed to 4'b0010, i.e. AXI3 Cacheable bit set. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Signed-off-by: Horia Geant? --- drivers/crypto/caam/ctrl.c | 5 +++-- drivers/crypto/caam/regs.h | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 598823746a3b..b924477c0d83 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -444,8 +444,9 @@ static int caam_probe(struct platform_device *pdev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - setbits32(&ctrl->mcr, MCFGR_WDENABLE | - (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | + MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? + MCFGR_LONG_PTR : 0)); /* * Read the Compile Time paramters and SCFGR to determine diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 672c97489505..5e643523de15 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -395,10 +395,16 @@ struct caam_ctrl { /* AXI read cache control */ #define MCFGR_ARCACHE_SHIFT 12 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) /* AXI write cache control */ #define MCFGR_AWCACHE_SHIFT 8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) /* AXI pipeline depth */ #define MCFGR_AXIPIPE_SHIFT 4