Message ID | 1450233580-58266-1-git-send-email-pingchao.yang@intel.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Herbert Xu |
Headers | show |
Am 16.12.2015 03:39, schrieb Yang Pingchao: > AE CTX bits should be 8-15 in CTX_ENABLES, so the mask > value 0xff should be left shifted 0x8. > > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> > --- > drivers/crypto/qat/qat_common/qat_hal.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c > index 45c1739..81bd1fe 100644 > --- a/drivers/crypto/qat/qat_common/qat_hal.c > +++ b/drivers/crypto/qat/qat_common/qat_hal.c > @@ -418,7 +418,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle, > > qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable); > qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active); > - if ((enable & (0xff >> CE_ENABLE_BITPOS)) || > + if ((enable & (0xff << CE_ENABLE_BITPOS)) || > (active & (1 << ACS_ABO_BITPOS))) > return 1; > else Is there any reason for using 0xff << CE_ENABLE_BITPOS instead of 0xff00 ? re, wh -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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On Wed, Dec 16, 2015 at 10:39:40AM +0800, Yang Pingchao wrote: > AE CTX bits should be 8-15 in CTX_ENABLES, so the mask > value 0xff should be left shifted 0x8. > > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> Patch applied. Thanks.
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c index 45c1739..81bd1fe 100644 --- a/drivers/crypto/qat/qat_common/qat_hal.c +++ b/drivers/crypto/qat/qat_common/qat_hal.c @@ -418,7 +418,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle, qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable); qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active); - if ((enable & (0xff >> CE_ENABLE_BITPOS)) || + if ((enable & (0xff << CE_ENABLE_BITPOS)) || (active & (1 << ACS_ABO_BITPOS))) return 1; else
AE CTX bits should be 8-15 in CTX_ENABLES, so the mask value 0xff should be left shifted 0x8. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> --- drivers/crypto/qat/qat_common/qat_hal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)