diff mbox

[3/3] drivers: crypto: Enable CPT options crypto for build

Message ID 1479481209-11475-4-git-send-email-gcherianv@gmail.com (mailing list archive)
State Changes Requested
Delegated to: Herbert Xu
Headers show

Commit Message

George Cherian Nov. 18, 2016, 3 p.m. UTC 
From: George Cherian <george.cherian@cavium.com>

Add the CPT options in crypto Kconfig and update the
crypto Makefile

Signed-off-by: George Cherian <george.cherian@cavium.com>
---
 drivers/crypto/Kconfig  | 1 +
 drivers/crypto/Makefile | 1 +
 2 files changed, 2 insertions(+)

Comments

kernel test robot Nov. 18, 2016, 8:44 p.m. UTC | #1 
Hi George,

[auto build test ERROR on cryptodev/master]
[also build test ERROR on v4.9-rc5 next-20161117]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/gcherianv-gmail-com/Add-Support-for-Cavium-Cryptographic-Accelerarion-Unit/20161119-005337
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

warning: (CRYPTO_DEV_CPT) selects HW_RANDOM_OCTEON which has unmet direct dependencies (HW_RANDOM && CAVIUM_OCTEON_SOC)
   In file included from drivers/crypto/cavium/cpt/cpt_common.h:27:0,
                    from drivers/crypto/cavium/cpt/cpt.h:12,
                    from drivers/crypto/cavium/cpt/cpt_main.c:19:
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:439:2: warning: no semicolon at end of struct or union
     } s;
     ^
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:608:3: error: expected ',', ';' or '}' before 'uint64_t'
      uint64_t reserved_0_5:6;
      ^~~~~~~~
   drivers/crypto/cavium/cpt/cpt_main.c:236:13: warning: 'cpt_enable_all_interrupts' defined but not used [-Wunused-function]
    static void cpt_enable_all_interrupts(struct cpt_device *cpt)
                ^~~~~~~~~~~~~~~~~~~~~~~~~
--
   In file included from drivers/crypto/cavium/cpt/cpt_common.h:27:0,
                    from drivers/crypto/cavium/cpt/cpt.h:12,
                    from drivers/crypto/cavium/cpt/cpt_pf_mbox.c:11:
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:439:2: warning: no semicolon at end of struct or union
     } s;
     ^
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:608:3: error: expected ',', ';' or '}' before 'uint64_t'
      uint64_t reserved_0_5:6;
      ^~~~~~~~
--
>> drivers/char/hw_random/octeon-rng.c:19:31: fatal error: asm/octeon/octeon.h: No such file or directory
    #include <asm/octeon/octeon.h>
                                  ^
   compilation terminated.

vim +608 drivers/crypto/cavium/cpt/cpt_hw_types.h

fcb2dbd1 George Cherian 2016-11-18  433  		uint64_t reserved_48_63:16;
fcb2dbd1 George Cherian 2016-11-18  434  		uint64_t bstatus:48
fcb2dbd1 George Cherian 2016-11-18  435  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  436  		uint64_t bstatus:48;
fcb2dbd1 George Cherian 2016-11-18  437  		uint64_t reserved_48_63:16;
fcb2dbd1 George Cherian 2016-11-18  438  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18 @439  	} s;
fcb2dbd1 George Cherian 2016-11-18  440  	struct cptx_pf_exe_bist_status_cn81xx {
fcb2dbd1 George Cherian 2016-11-18  441  #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  442  		uint64_t reserved_16_63:48;
fcb2dbd1 George Cherian 2016-11-18  443  		uint64_t bstatus:16;
fcb2dbd1 George Cherian 2016-11-18  444  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  445  		uint64_t bstatus:16;
fcb2dbd1 George Cherian 2016-11-18  446  		uint64_t reserved_16_63:48;
fcb2dbd1 George Cherian 2016-11-18  447  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  448  	} cn81xx;
fcb2dbd1 George Cherian 2016-11-18  449  };
fcb2dbd1 George Cherian 2016-11-18  450  
fcb2dbd1 George Cherian 2016-11-18  451  /**
fcb2dbd1 George Cherian 2016-11-18  452   * Register (NCB) cpt#_pf_exe_ctl
fcb2dbd1 George Cherian 2016-11-18  453   *
fcb2dbd1 George Cherian 2016-11-18  454   * CPT PF Engine Control Register
fcb2dbd1 George Cherian 2016-11-18  455   * This register enables the engines.
fcb2dbd1 George Cherian 2016-11-18  456   * cptx_pf_exe_ctl_s
fcb2dbd1 George Cherian 2016-11-18  457   * Word0
fcb2dbd1 George Cherian 2016-11-18  458   *  enable:64 [63:0](R/W) Individual enables for each of the engines.
fcb2dbd1 George Cherian 2016-11-18  459   */
fcb2dbd1 George Cherian 2016-11-18  460  union cptx_pf_exe_ctl {
fcb2dbd1 George Cherian 2016-11-18  461  	uint64_t u;
fcb2dbd1 George Cherian 2016-11-18  462  	struct cptx_pf_exe_ctl_s {
fcb2dbd1 George Cherian 2016-11-18  463  #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  464  		uint64_t enable:64;
fcb2dbd1 George Cherian 2016-11-18  465  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  466  		uint64_t enable:64;
fcb2dbd1 George Cherian 2016-11-18  467  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  468  	} s;
fcb2dbd1 George Cherian 2016-11-18  469  };
fcb2dbd1 George Cherian 2016-11-18  470  
fcb2dbd1 George Cherian 2016-11-18  471  /**
fcb2dbd1 George Cherian 2016-11-18  472   * Register (NCB) cpt#_pf_q#_ctl
fcb2dbd1 George Cherian 2016-11-18  473   *
fcb2dbd1 George Cherian 2016-11-18  474   * CPT Queue Control Register
fcb2dbd1 George Cherian 2016-11-18  475   * This register configures queues. This register should be changed only
fcb2dbd1 George Cherian 2016-11-18  476   * when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
fcb2dbd1 George Cherian 2016-11-18  477   * cptx_pf_qx_ctl_s
fcb2dbd1 George Cherian 2016-11-18  478   * Word0
fcb2dbd1 George Cherian 2016-11-18  479   *  reserved_60_63:4 [63:60] reserved.
fcb2dbd1 George Cherian 2016-11-18  480   *  aura:12; [59:48](R/W) Guest-aura for returning this queue's
fcb2dbd1 George Cherian 2016-11-18  481   *	instruction-chunk buffers to FPA. Only used when [INST_FREE] is set.
fcb2dbd1 George Cherian 2016-11-18  482   *	For the FPA to not discard the request, FPA_PF_MAP() must map
fcb2dbd1 George Cherian 2016-11-18  483   *	[AURA] and CPT()_PF_Q()_GMCTL[GMID] as valid.
fcb2dbd1 George Cherian 2016-11-18  484   *  reserved_45_47:3 [47:45] reserved.
fcb2dbd1 George Cherian 2016-11-18  485   *  size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per
fcb2dbd1 George Cherian 2016-11-18  486   *	command buffer segment. Must be 8*n + 1, where n is the number of
fcb2dbd1 George Cherian 2016-11-18  487   *	instructions per buffer segment.
fcb2dbd1 George Cherian 2016-11-18  488   *  reserved_11_31:21 [31:11] Reserved.
fcb2dbd1 George Cherian 2016-11-18  489   *  cont_err:1 [10:10](R/W) Continue on error.
fcb2dbd1 George Cherian 2016-11-18  490   *	0 = When CPT()_VQ()_MISC_INT[NWRP], CPT()_VQ()_MISC_INT[IRDE] or
fcb2dbd1 George Cherian 2016-11-18  491   *	CPT()_VQ()_MISC_INT[DOVF] are set by hardware or software via
fcb2dbd1 George Cherian 2016-11-18  492   *	CPT()_VQ()_MISC_INT_W1S, then CPT()_VQ()_CTL[ENA] is cleared.  Due to
fcb2dbd1 George Cherian 2016-11-18  493   *	pipelining, additional instructions may have been processed between the
fcb2dbd1 George Cherian 2016-11-18  494   *	instruction causing the error and the next instruction in the disabled
fcb2dbd1 George Cherian 2016-11-18  495   *	queue (the instruction at CPT()_VQ()_SADDR).
fcb2dbd1 George Cherian 2016-11-18  496   *	1 = Ignore errors and continue processing instructions.
fcb2dbd1 George Cherian 2016-11-18  497   *	For diagnostic use only.
fcb2dbd1 George Cherian 2016-11-18  498   *  inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the
fcb2dbd1 George Cherian 2016-11-18  499   *	end of an instruction chunk, that chunk will be freed to the FPA.
fcb2dbd1 George Cherian 2016-11-18  500   *  inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions,
fcb2dbd1 George Cherian 2016-11-18  501   *	instruction next chunk pointers, and result structures are stored in
fcb2dbd1 George Cherian 2016-11-18  502   *	big-endian format in memory.
fcb2dbd1 George Cherian 2016-11-18  503   *  iqb_ldwb:1 [7:7](R/W) Instruction load don't write back.
fcb2dbd1 George Cherian 2016-11-18  504   *	0 = The hardware issues NCB transient load (LDT) towards the cache,
fcb2dbd1 George Cherian 2016-11-18  505   *	which if the line hits and is is dirty will cause the line to be
fcb2dbd1 George Cherian 2016-11-18  506   *	written back before being replaced.
fcb2dbd1 George Cherian 2016-11-18  507   *	1 = The hardware issues NCB LDWB read-and-invalidate command towards
fcb2dbd1 George Cherian 2016-11-18  508   *	the cache when fetching the last word of instructions; as a result the
fcb2dbd1 George Cherian 2016-11-18  509   *	line will not be written back when replaced.  This improves
fcb2dbd1 George Cherian 2016-11-18  510   *	performance, but software must not read the instructions after they are
fcb2dbd1 George Cherian 2016-11-18  511   *	posted to the hardware.	Reads that do not consume the last word of a
fcb2dbd1 George Cherian 2016-11-18  512   *	cache line always use LDI.
fcb2dbd1 George Cherian 2016-11-18  513   *  reserved_4_6:3 [6:4] Reserved.
fcb2dbd1 George Cherian 2016-11-18  514   *  grp:3; [3:1](R/W) Engine group.
fcb2dbd1 George Cherian 2016-11-18  515   *  pri:1; [0:0](R/W) Queue priority.
fcb2dbd1 George Cherian 2016-11-18  516   *	1 = This queue has higher priority. Round-robin between higher
fcb2dbd1 George Cherian 2016-11-18  517   *	priority queues.
fcb2dbd1 George Cherian 2016-11-18  518   *	0 = This queue has lower priority. Round-robin between lower
fcb2dbd1 George Cherian 2016-11-18  519   *	priority queues.
fcb2dbd1 George Cherian 2016-11-18  520   */
fcb2dbd1 George Cherian 2016-11-18  521  union cptx_pf_qx_ctl {
fcb2dbd1 George Cherian 2016-11-18  522  	uint64_t u;
fcb2dbd1 George Cherian 2016-11-18  523  	struct cptx_pf_qx_ctl_s {
fcb2dbd1 George Cherian 2016-11-18  524  #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  525  		uint64_t reserved_60_63:4;
fcb2dbd1 George Cherian 2016-11-18  526  		uint64_t aura:12;
fcb2dbd1 George Cherian 2016-11-18  527  		uint64_t reserved_45_47:3;
fcb2dbd1 George Cherian 2016-11-18  528  		uint64_t size:13;
fcb2dbd1 George Cherian 2016-11-18  529  		uint64_t reserved_11_31:21;
fcb2dbd1 George Cherian 2016-11-18  530  		uint64_t cont_err:1;
fcb2dbd1 George Cherian 2016-11-18  531  		uint64_t inst_free:1;
fcb2dbd1 George Cherian 2016-11-18  532  		uint64_t inst_be:1;
fcb2dbd1 George Cherian 2016-11-18  533  		uint64_t iqb_ldwb:1;
fcb2dbd1 George Cherian 2016-11-18  534  		uint64_t reserved_4_6:3;
fcb2dbd1 George Cherian 2016-11-18  535  		uint64_t grp:3;
fcb2dbd1 George Cherian 2016-11-18  536  		uint64_t pri:1;
fcb2dbd1 George Cherian 2016-11-18  537  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  538  		uint64_t pri:1;
fcb2dbd1 George Cherian 2016-11-18  539  		uint64_t grp:3;
fcb2dbd1 George Cherian 2016-11-18  540  		uint64_t reserved_4_6:3;
fcb2dbd1 George Cherian 2016-11-18  541  		uint64_t iqb_ldwb:1;
fcb2dbd1 George Cherian 2016-11-18  542  		uint64_t inst_be:1;
fcb2dbd1 George Cherian 2016-11-18  543  		uint64_t inst_free:1;
fcb2dbd1 George Cherian 2016-11-18  544  		uint64_t cont_err:1;
fcb2dbd1 George Cherian 2016-11-18  545  		uint64_t reserved_11_31:21;
fcb2dbd1 George Cherian 2016-11-18  546  		uint64_t size:13;
fcb2dbd1 George Cherian 2016-11-18  547  		uint64_t reserved_45_47:3;
fcb2dbd1 George Cherian 2016-11-18  548  		uint64_t aura:12;
fcb2dbd1 George Cherian 2016-11-18  549  		uint64_t reserved_60_63:4;
fcb2dbd1 George Cherian 2016-11-18  550  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  551  	} s;
fcb2dbd1 George Cherian 2016-11-18  552      /* struct cptx_pf_qx_ctl_s cn; */
fcb2dbd1 George Cherian 2016-11-18  553  };
fcb2dbd1 George Cherian 2016-11-18  554  
fcb2dbd1 George Cherian 2016-11-18  555  /**
fcb2dbd1 George Cherian 2016-11-18  556   * Register (NCB) cpt#_pf_g#_en
fcb2dbd1 George Cherian 2016-11-18  557   *
fcb2dbd1 George Cherian 2016-11-18  558   * CPT PF Group Control Register
fcb2dbd1 George Cherian 2016-11-18  559   * This register configures engine groups.
fcb2dbd1 George Cherian 2016-11-18  560   * cptx_pf_gx_en_s
fcb2dbd1 George Cherian 2016-11-18  561   * Word0
fcb2dbd1 George Cherian 2016-11-18  562   *  en: 64; [63:0](R/W/H) Engine group enable. One bit corresponds to each
fcb2dbd1 George Cherian 2016-11-18  563   *	engine, with the bit set to indicate this engine can service this group.
fcb2dbd1 George Cherian 2016-11-18  564   *	Bits corresponding to unimplemented engines read as zero, i.e. only bit
fcb2dbd1 George Cherian 2016-11-18  565   *	numbers	less than CPT()_PF_CONSTANTS[AE] + CPT()_PF_CONSTANTS[SE] are
fcb2dbd1 George Cherian 2016-11-18  566   *	writable. AE engine bits follow SE engine bits.
fcb2dbd1 George Cherian 2016-11-18  567   *	E.g. if CPT()_PF_CONSTANTS[AE] = 0x1, and CPT()_PF_CONSTANTS[SE] = 0x2,
fcb2dbd1 George Cherian 2016-11-18  568   *	then bits <2:0> are read/writable with bit <2> corresponding to AE<0>,
fcb2dbd1 George Cherian 2016-11-18  569   *	and bit <1> to SE<1>, and bit<0> to SE<0>. Before disabling an engine,
fcb2dbd1 George Cherian 2016-11-18  570   *	the corresponding bit in each group must be cleared. CPT()_PF_EXEC_BUSY
fcb2dbd1 George Cherian 2016-11-18  571   *	can then be polled to determing when the engine becomes	idle.
fcb2dbd1 George Cherian 2016-11-18  572   *	At the point, the engine can be disabled.
fcb2dbd1 George Cherian 2016-11-18  573   */
fcb2dbd1 George Cherian 2016-11-18  574  union cptx_pf_gx_en {
fcb2dbd1 George Cherian 2016-11-18  575  	uint64_t u;
fcb2dbd1 George Cherian 2016-11-18  576  	struct cptx_pf_gx_en_s {
fcb2dbd1 George Cherian 2016-11-18  577  #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  578  		uint64_t en:64;
fcb2dbd1 George Cherian 2016-11-18  579  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  580  		uint64_t en:64;
fcb2dbd1 George Cherian 2016-11-18  581  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  582  	} s;
fcb2dbd1 George Cherian 2016-11-18  583  };
fcb2dbd1 George Cherian 2016-11-18  584  
fcb2dbd1 George Cherian 2016-11-18  585  /**
fcb2dbd1 George Cherian 2016-11-18  586   * Register (NCB) cpt#_vq#_saddr
fcb2dbd1 George Cherian 2016-11-18  587   *
fcb2dbd1 George Cherian 2016-11-18  588   * CPT Queue Starting Buffer Address Registers
fcb2dbd1 George Cherian 2016-11-18  589   * These registers set the instruction buffer starting address.
fcb2dbd1 George Cherian 2016-11-18  590   * cptx_vqx_saddr_s
fcb2dbd1 George Cherian 2016-11-18  591   * Word0
fcb2dbd1 George Cherian 2016-11-18  592   *  reserved_49_63:15 [63:49] Reserved.
fcb2dbd1 George Cherian 2016-11-18  593   *  ptr:43 [48:6](R/W/H) Instruction buffer IOVA <48:6> (64-byte aligned).
fcb2dbd1 George Cherian 2016-11-18  594   *	When written, it is the initial buffer starting address; when read,
fcb2dbd1 George Cherian 2016-11-18  595   *	it is the next read pointer to be requested from L2C. The PTR field
fcb2dbd1 George Cherian 2016-11-18  596   *	is overwritten with the next pointer each time that the command buffer
fcb2dbd1 George Cherian 2016-11-18  597   *	segment is exhausted. New commands will then be read from the newly
fcb2dbd1 George Cherian 2016-11-18  598   *	specified command buffer pointer.
fcb2dbd1 George Cherian 2016-11-18  599   *  reserved_0_5:6 [5:0] Reserved.
fcb2dbd1 George Cherian 2016-11-18  600   *
fcb2dbd1 George Cherian 2016-11-18  601   */
fcb2dbd1 George Cherian 2016-11-18  602  union cptx_vqx_saddr {
fcb2dbd1 George Cherian 2016-11-18  603  	uint64_t u;
fcb2dbd1 George Cherian 2016-11-18  604  	struct cptx_vqx_saddr_s {
fcb2dbd1 George Cherian 2016-11-18  605  #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  606  		uint64_t reserved_49_63:15;
fcb2dbd1 George Cherian 2016-11-18  607  		uint64_t ptr:43
fcb2dbd1 George Cherian 2016-11-18 @608  		uint64_t reserved_0_5:6;
fcb2dbd1 George Cherian 2016-11-18  609  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  610  		uint64_t reserved_0_5:6;
fcb2dbd1 George Cherian 2016-11-18  611  		uint64_t ptr:43;

:::::: The code at line 608 was first introduced by commit
:::::: fcb2dbd14b3247c53056bc2b78e907c569da1d44 drivers: crypto: Add Support for Octeon-tx CPT Engine

:::::: TO: George Cherian <george.cherian@cavium.com>
:::::: CC: 0day robot <fengguang.wu@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4d2b81f..15f9040 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -484,6 +484,7 @@  config CRYPTO_DEV_MXS_DCP
 	  will be called mxs-dcp.
 
 source "drivers/crypto/qat/Kconfig"
+source "drivers/crypto/cavium/cpt/Kconfig"
 
 config CRYPTO_DEV_QCE
 	tristate "Qualcomm crypto engine accelerator"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index ad7250f..dd33290 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -32,3 +32,4 @@  obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
+obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/