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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0301MB2003 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Generic GCM is likely to end up using a hardware accelerator to do part of the job. Allocating hash, iv and result in a contiguous memory area increases the risk of dma mapping multiple ranges on the same cacheline. Also having dma and cpu written data on the same cacheline will cause coherence issues. Signed-off-by: Radu Solea --- Hi! I've encountered cache coherence issues when using GCM with CAAM and this was one way of fixing them but it has its drawbacks. Another would be to allocate each element instead of all at once, but that only decreases the likelyhood of this happening. Does anyone know of a better way of fixing this? Thanks, Radu. crypto/gcm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/crypto/gcm.c b/crypto/gcm.c index b7ad808..657eefe 100644 --- a/crypto/gcm.c +++ b/crypto/gcm.c @@ -117,9 +117,9 @@ static int crypto_gcm_setkey(struct crypto_aead *aead, const u8 *key, struct crypto_skcipher *ctr = ctx->ctr; struct { be128 hash; - u8 iv[16]; + u8 iv[16] ____cacheline_aligned; - struct crypto_gcm_setkey_result result; + struct crypto_gcm_setkey_result result ____cacheline_aligned; struct scatterlist sg[1]; struct skcipher_request req;