diff mbox series

crypto: hisilicon - update SEC driver module parameter

Message ID 1591624871-49173-1-git-send-email-liulongfang@huawei.com (mailing list archive)
State Accepted
Delegated to: Herbert Xu
Headers show
Series crypto: hisilicon - update SEC driver module parameter | expand

Commit Message

liulongfang June 8, 2020, 2:01 p.m. UTC
As stress-ng running SEC engine on the Ubuntu OS,
we found that SEC only supports two threads each with one TFM
based on the default module parameter 'ctx_q_num'.
If running more threads, stress-ng will fail since it cannot
get more TFMs.

In order to fix this, we adjusted the default values
of the module parameters to support more TFMs.

Signed-off-by: Longfang Liu <liulongfang@huawei.com>
Signed-off-by: Zaibo Xu <xuzaibo@huawei.com>
---
 drivers/crypto/hisilicon/sec2/sec_main.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

liulongfang June 17, 2020, 2:01 a.m. UTC | #1
On 2020/6/8 22:01, Longfang Liu Wrote:
> As stress-ng running SEC engine on the Ubuntu OS,
> we found that SEC only supports two threads each with one TFM
> based on the default module parameter 'ctx_q_num'.
> If running more threads, stress-ng will fail since it cannot
> get more TFMs.
>
> In order to fix this, we adjusted the default values
> of the module parameters to support more TFMs.
>
> Signed-off-by: Longfang Liu <liulongfang@huawei.com>
> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com>
> ---
>  drivers/crypto/hisilicon/sec2/sec_main.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
> index a4cb58b..57de51f 100644
> --- a/drivers/crypto/hisilicon/sec2/sec_main.c
> +++ b/drivers/crypto/hisilicon/sec2/sec_main.c
> @@ -30,9 +30,9 @@
>  
>  #define SEC_SQE_SIZE			128
>  #define SEC_SQ_SIZE			(SEC_SQE_SIZE * QM_Q_DEPTH)
> -#define SEC_PF_DEF_Q_NUM		64
> +#define SEC_PF_DEF_Q_NUM		256
>  #define SEC_PF_DEF_Q_BASE		0
> -#define SEC_CTX_Q_NUM_DEF		24
> +#define SEC_CTX_Q_NUM_DEF		2
>  #define SEC_CTX_Q_NUM_MAX		32
>  
>  #define SEC_CTRL_CNT_CLR_CE		0x301120
> @@ -191,7 +191,7 @@ static const struct kernel_param_ops sec_ctx_q_num_ops = {
>  };
>  static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
>  module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
> -MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)");
> +MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
>  
>  static const struct kernel_param_ops vfs_num_ops = {
>  	.set = vfs_num_set,

Hi ALL,

 I'd appreciate any comments on this patch
from crypto related people.

Thanks,

Longfang
Herbert Xu June 18, 2020, 7:57 a.m. UTC | #2
On Mon, Jun 08, 2020 at 10:01:11PM +0800, Longfang Liu wrote:
> As stress-ng running SEC engine on the Ubuntu OS,
> we found that SEC only supports two threads each with one TFM
> based on the default module parameter 'ctx_q_num'.
> If running more threads, stress-ng will fail since it cannot
> get more TFMs.
> 
> In order to fix this, we adjusted the default values
> of the module parameters to support more TFMs.
> 
> Signed-off-by: Longfang Liu <liulongfang@huawei.com>
> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com>
> ---
>  drivers/crypto/hisilicon/sec2/sec_main.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Patch applied.  Thanks.
diff mbox series

Patch

diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index a4cb58b..57de51f 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -30,9 +30,9 @@ 
 
 #define SEC_SQE_SIZE			128
 #define SEC_SQ_SIZE			(SEC_SQE_SIZE * QM_Q_DEPTH)
-#define SEC_PF_DEF_Q_NUM		64
+#define SEC_PF_DEF_Q_NUM		256
 #define SEC_PF_DEF_Q_BASE		0
-#define SEC_CTX_Q_NUM_DEF		24
+#define SEC_CTX_Q_NUM_DEF		2
 #define SEC_CTX_Q_NUM_MAX		32
 
 #define SEC_CTRL_CNT_CLR_CE		0x301120
@@ -191,7 +191,7 @@  static const struct kernel_param_ops sec_ctx_q_num_ops = {
 };
 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
-MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)");
+MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
 
 static const struct kernel_param_ops vfs_num_ops = {
 	.set = vfs_num_set,