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Thu, 13 Apr 2017 16:47:00 +0000 Subject: [PATCH V2 1/2] crypto: ccp - Use only the relevant interrupt bits From: Gary R Hook To: CC: , , Date: Thu, 13 Apr 2017 11:46:46 -0500 Message-ID: <20170413164646.11624.66163.stgit@taos> In-Reply-To: <20170413164352.11624.84058.stgit@taos> References: <20170413164352.11624.84058.stgit@taos> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: MWHPR21CA0054.namprd21.prod.outlook.com (10.172.93.144) To BY1PR12MB0471.namprd12.prod.outlook.com (10.162.147.148) X-MS-Office365-Filtering-Correlation-Id: 8fed500f-bb29-42ad-c4fd-08d4828cb4f5 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:BY1PR12MB0471; X-Microsoft-Exchange-Diagnostics: 1; BY1PR12MB0471; 3:6Eb6y0EmCiGycMzK024+Yx8Xil4iGhM79AwBLrJTZqaF9oqLxmOnj+Q5TcmuzQYbO82otSNJMlKoumehnqAaKbZSYstdQsTzesDbh4HjIrtmRZd/PXul5KJNzOLAizGQFEs1MEWAZ1HAvRb+O3S5uXr1e2iU/xSdOYrjCyY1ggyFoxvV00T3NWoAKcj30aUL1MPOycjYrKr42xmbS9a9kNvq//i+8xdOGbryCJqFlEEQ9g+78Mby02eaUc6d2UX7zEkrlJm3yZySe30pUjQ/CummZxHOkrgO8YBiiae/vyFVTsiIRmiYzHMDoHJOzK3yWytkToNuyPjOA+Z00aH8JL8IY0j0YOlMwuh2AAIJ/ys=; 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20:tIOCoC650p34mCF2+VOU2iB9mD0wfpj1ulXVtrkhacZtSNny4PaKNGOnZqx0porf8XW5aCDcTMDWoVyEIKfV88wwOjnIacpiRUTw8XSAq0MofQwphwT5rw6++cZFdpaQqrib90hP9pioMvnIJg0v9CPOIxbozBe2uEuBlsPxe/BQmFcDUuCMcBrUclKm20jlMlnVBSyNkL5wt7+ft54CZtjA9vIP5oH+Qdy6rTjltqm2x1O3Rpi2JTK1J/wFrHA4 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2017 16:47:00.3055 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB0471 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Each CCP queue can product interrupts for 4 conditions: operation complete, queue empty, error, and queue stopped. This driver only works with completion and error events. Signed-off-by: Gary R Hook --- drivers/crypto/ccp/ccp-dev-v5.c | 9 +++++---- drivers/crypto/ccp/ccp-dev.h | 5 ++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/ccp/ccp-dev-v5.c b/drivers/crypto/ccp/ccp-dev-v5.c index e03d06a..c7972e7 100644 --- a/drivers/crypto/ccp/ccp-dev-v5.c +++ b/drivers/crypto/ccp/ccp-dev-v5.c @@ -801,7 +801,7 @@ static int ccp5_init(struct ccp_device *ccp) ioread32(cmd_q->reg_status); /* Clear the interrupts */ - iowrite32(ALL_INTERRUPTS, cmd_q->reg_interrupt_status); + iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_interrupt_status); } dev_dbg(dev, "Requesting an IRQ...\n"); @@ -882,7 +882,7 @@ static int ccp5_init(struct ccp_device *ccp) /* Enable interrupts */ for (i = 0; i < ccp->cmd_q_count; i++) { cmd_q = &ccp->cmd_q[i]; - iowrite32(ALL_INTERRUPTS, cmd_q->reg_int_enable); + iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_int_enable); } dev_dbg(dev, "Registering device...\n"); @@ -942,7 +942,7 @@ static void ccp5_destroy(struct ccp_device *ccp) iowrite32(cmd_q->qcontrol & ~CMD5_Q_RUN, cmd_q->reg_control); /* Disable the interrupts */ - iowrite32(ALL_INTERRUPTS, cmd_q->reg_interrupt_status); + iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_interrupt_status); /* Clear the interrupt status */ iowrite32(0x00, cmd_q->reg_int_enable); @@ -1002,7 +1002,8 @@ static irqreturn_t ccp5_irq_handler(int irq, void *data) cmd_q->int_rcvd = 1; /* Acknowledge the interrupt and wake the kthread */ - iowrite32(ALL_INTERRUPTS, cmd_q->reg_interrupt_status); + iowrite32(SUPPORTED_INTERRUPTS, + cmd_q->reg_interrupt_status); wake_up_interruptible(&cmd_q->int_queue); } } diff --git a/drivers/crypto/ccp/ccp-dev.h b/drivers/crypto/ccp/ccp-dev.h index 191274d..2dfec01 100644 --- a/drivers/crypto/ccp/ccp-dev.h +++ b/drivers/crypto/ccp/ccp-dev.h @@ -109,9 +109,8 @@ #define INT_COMPLETION 0x1 #define INT_ERROR 0x2 #define INT_QUEUE_STOPPED 0x4 -#define ALL_INTERRUPTS (INT_COMPLETION| \ - INT_ERROR| \ - INT_QUEUE_STOPPED) +#define INT_EMPTY_QUEUE 0x8 +#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR) #define LSB_REGION_WIDTH 5 #define MAX_LSB_CNT 8