From patchwork Tue Jan 30 15:29:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 10192013 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6BF0260375 for ; Tue, 30 Jan 2018 15:31:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B0AE288EA for ; Tue, 30 Jan 2018 15:31:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FC6628903; Tue, 30 Jan 2018 15:31:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2762288EF for ; Tue, 30 Jan 2018 15:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753157AbeA3Pa7 (ORCPT ); Tue, 30 Jan 2018 10:30:59 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:58730 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753005AbeA3Pa6 (ORCPT ); Tue, 30 Jan 2018 10:30:58 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 4BAD073EE548E; Tue, 30 Jan 2018 23:30:45 +0800 (CST) Received: from J00421895.china.huawei.com (10.202.226.42) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.361.1; Tue, 30 Jan 2018 23:30:36 +0800 From: Jonathan Cameron To: CC: , , Herbert Xu , "David S . Miller" , =?UTF-8?q?Stephan=20M=C3=BCller?= , , Mark Brown , Xiongfeng Wang , Jonathan Cameron Subject: [RFC PATCH 1/3] dt-bindings: Add bindings for Hisilicon SEC crypto accelerators. Date: Tue, 30 Jan 2018 15:29:51 +0000 Message-ID: <20180130152953.14068-2-jonathan.cameron@huawei.com> X-Mailer: git-send-email 2.16.1.windows.1 In-Reply-To: <20180130152953.14068-1-jonathan.cameron@huawei.com> References: <20180130152953.14068-1-jonathan.cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.42] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jonathan Cameron The hip06 and hip07 SoCs contain a number of these crypto units which accelerate AES and DES operations. Signed-off-by: Jonathan Cameron --- .../bindings/crypto/hisilicon,hip07-sec.txt | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt new file mode 100644 index 000000000000..bf81118e560c --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt @@ -0,0 +1,71 @@ +* Hisilicon hip07 Security Accelerator (SEC) + +Required properties: +- compatible: Must contain one of + - "hisilicon,hip06-sec" + - "hisilicon,hip07-sec" +- #address-cells: Must be <2> as 64 bit addresses in reg. +- #size-cells: Must be <2> as 64 bit lengths in reg. +- reg: Memory addresses and lengths of the memory regions used by the driver. + Region 0 has registers to control the backend processing engines. + Region 1 has registers for functionality common to all queues. + Regions 2-18 have registers for the individual queues which are isolated + both in hardware and within the driver. +- interrupts: Interrupt specifiers. + Refer to interrupt-controller/interrupts.txt for generic interrupt client node + bindings. + Interrupt 0 is for the SEC unit error queue. + Interrupt 2N + 1 is the completion interrupt for queue N. + Interrupt 2N + 2 is the error interrupt for queue N. +- dma-coherent: The driver assumes coherent dma is possible. + +Optional properties: +- iommus: The SEC units are behind smmu-v3 iommus. + Refer to iommu/arm,smmu-v3.txt for more information. + +Example: +Second socket, first unit chosen to illustrate need for 64 bit addresses. + +p1_sec_a: sec@d2000000 { + compatible = "hisilicon,hip07-sec"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x400 0xd0000000 0x0 0x10000 + 0x400 0xd2000000 0x0 0x10000 + 0x400 0xd2010000 0x0 0x10000 + 0x400 0xd2020000 0x0 0x10000 + 0x400 0xd2030000 0x0 0x10000 + 0x400 0xd2040000 0x0 0x10000 + 0x400 0xd2050000 0x0 0x10000 + 0x400 0xd2060000 0x0 0x10000 + 0x400 0xd2070000 0x0 0x10000 + 0x400 0xd2080000 0x0 0x10000 + 0x400 0xd2090000 0x0 0x10000 + 0x400 0xd20a0000 0x0 0x10000 + 0x400 0xd20b0000 0x0 0x10000 + 0x400 0xd20c0000 0x0 0x10000 + 0x400 0xd20d0000 0x0 0x10000 + 0x400 0xd20e0000 0x0 0x10000 + 0x400 0xd20f0000 0x0 0x10000 + 0x400 0xd2100000 0x0 0x10000>; + interrupt-parent = <&p1_mbigen_sec_a>; + iommus = <&p1_smmu_alg_a 0x600>; + dma-coherent; + interrupts = <576 4>, + <577 1>,<578 4>, + <579 1>,<580 4>, + <581 1>,<582 4>, + <583 1>,<584 4>, + <585 1>,<586 4>, + <587 1>,<588 4>, + <589 1>,<590 4>, + <591 1>,<592 4>, + <593 1>,<594 4>, + <595 1>,<596 4>, + <597 1>,<598 4>, + <599 1>,<600 4>, + <601 1>,<602 4>, + <603 1>,<604 4>, + <605 1>,<606 4>, + <607 1>,<608 4>; +};