From patchwork Mon Aug 27 11:02:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 10576951 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A80417DE for ; Mon, 27 Aug 2018 11:03:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DFF229523 for ; Mon, 27 Aug 2018 11:03:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 62AFF2963D; Mon, 27 Aug 2018 11:03:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5AA8D295DD for ; Mon, 27 Aug 2018 11:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727098AbeH0OtP (ORCPT ); Mon, 27 Aug 2018 10:49:15 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:45045 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727092AbeH0OtO (ORCPT ); Mon, 27 Aug 2018 10:49:14 -0400 Received: by mail-ed1-f66.google.com with SMTP id s10-v6so10115911edb.11 for ; Mon, 27 Aug 2018 04:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oTakMaiOebK5l3wbEWRh64Nq6kIU7IgNvjz7uyzmuwA=; b=jn6/3+OxOGwmvIFxTYpbSRgKOXuI7apBvxHgX8ipNy0TVAvz0eTHh9MNMGRwB1OqX8 NvbEfc+1acMAk5iURWGZcozMcVtoROK/kWS2espfMemsS29uZUKNyazEBOz7dNjguZ++ GGD6rxwtYc3tkLWMlwLOHIzaKnzHsHg1fqYAk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oTakMaiOebK5l3wbEWRh64Nq6kIU7IgNvjz7uyzmuwA=; b=eKBz0AQpkKDOVa7ONxtsC+9y0iJ2YafzJqCGVvuBvsCPxlqY+mdudQZ2HOCxeam5dK yxoy50BIW/erl8p5htxKQzhBcDA7/M3gO+AvT8lXf0zioI3B0UsIbMw8YhNvwIX8SwKg OItxb/KO1lequTfejIk5FHUtvxaGQ/We8qeH91o7pfjPLtr2yccuHtM+OckRrCJwfICz UYrTEnHQIkXBNSQlTjTgqPPzR18Jb/IZ6BspePnBYWZkyrzrCDPmOwywn8/XhAFkUKkk PbgdAR4VQ2a7nKFtW5HN8Lz2C9GuNt6kGDbPLMkw/5tq0ZhqzgPaHZn47CoL+rmxeqLD Tc+w== X-Gm-Message-State: APzg51DBanj5ALhfZtZ85H8JU35g++RCEnPu1p+fJRmVmg1GmmpzX3Hv xYKPZ/RkLwlA/Slw/azHND7QSg== X-Google-Smtp-Source: ANB0VdaNlQQXTe7ZyRNSXz0CpEdAuQ5F2duo21GJzpkBAaoE+YIUDLAZpmGV2G67TlEncXfO5EsZOg== X-Received: by 2002:a50:93a6:: with SMTP id o35-v6mr16577539eda.300.1535367782373; Mon, 27 Aug 2018 04:03:02 -0700 (PDT) Received: from rev02.home ([2a02:a212:9283:9800:24b9:e2d6:9acc:50dd]) by smtp.gmail.com with ESMTPSA id r2-v6sm3114344eda.89.2018.08.27.04.03.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Aug 2018 04:03:01 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org Cc: will.deacon@arm.com, catalin.marinas@arm.com, herbert@gondor.apana.org.au, ebiggers@google.com, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org, Ard Biesheuvel Subject: [PATCH 2/4] arm64: cpufeature: add feature for CRC32 instructions Date: Mon, 27 Aug 2018 13:02:43 +0200 Message-Id: <20180827110245.14812-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180827110245.14812-1-ard.biesheuvel@linaro.org> References: <20180827110245.14812-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a CRC32 feature bit and wire it up to the CPU id register so we will be able to use alternatives patching for CRC32 operations. Signed-off-by: Ard Biesheuvel Acked-by: Will Deacon --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpufeature.c | 9 +++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index ae1f70450fb2..9932aca9704b 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -51,7 +51,8 @@ #define ARM64_SSBD 30 #define ARM64_MISMATCHED_CACHE_TYPE 31 #define ARM64_HAS_STAGE2_FWB 32 +#define ARM64_HAS_CRC32 33 -#define ARM64_NCAPS 33 +#define ARM64_NCAPS 34 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e238b7932096..7626b80128f5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1222,6 +1222,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .cpu_enable = cpu_enable_hw_dbm, }, #endif + { + .desc = "CRC32 instructions", + .capability = ARM64_HAS_CRC32, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64ISAR0_EL1, + .field_pos = ID_AA64ISAR0_CRC32_SHIFT, + .min_field_value = 1, + }, {}, };