| Message ID | 20190428083322.26175-1-gilad@benyossef.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | crypto: ccree: use a proper le32 type for le32 val | expand |
On Sun, Apr 28, 2019 at 11:33:22AM +0300, Gilad Ben-Yossef wrote: > We build an explicit little endian value from the IDR register > values. Use a proper le32 type to mark the var as such to > satisfy Sparse. > > Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> > Reported-by: kbuild test robot <lkp@intel.com> > Fixes: dcf6285d18ea1 ("crypto: ccree - add CID and PID support") > --- > drivers/crypto/ccree/cc_driver.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Patch applied. Thanks.
diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c index 902f196d4be1..208957726cff 100644 --- a/drivers/crypto/ccree/cc_driver.c +++ b/drivers/crypto/ccree/cc_driver.c @@ -103,7 +103,7 @@ static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets) int i; union { u8 regs[CC_NUM_IDRS]; - u32 val; + __le32 val; } idr; for (i = 0; i < CC_NUM_IDRS; ++i)
We build an explicit little endian value from the IDR register values. Use a proper le32 type to mark the var as such to satisfy Sparse. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Reported-by: kbuild test robot <lkp@intel.com> Fixes: dcf6285d18ea1 ("crypto: ccree - add CID and PID support") --- drivers/crypto/ccree/cc_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)