| Message ID | 20190830210139.7028-1-andrew.smirnov@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | arm64: dts: imx8mq: Add CAAM node | expand |
On 8/31/2019 12:01 AM, Andrey Smirnov wrote: > Add node for CAAM - Cryptographic Acceleration and Assurance Module. > > Signed-off-by: Horia Geantă <horia.geanta@nxp.com> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > Cc: Cory Tusar <cory.tusar@zii.aero> > Cc: Chris Healy <cphealy@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Iuliana Prodan <iuliana.prodan@nxp.com> > Cc: linux-crypto@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > > Shawn: > > Just a bit of a context: as per this thread > https://lore.kernel.org/linux-crypto/20190830131547.GA27480@gondor.apana.org.au/ > I am hoping I can get and Ack from you for this patch, so it can go > via cryptodev tree. > Could we please get an Ack in time for v5.4? Thanks, Horia > Thanks, > Andrey Smirnov > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index d09b808eff87..752d5a61878c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -728,6 +728,36 @@ > status = "disabled"; > }; > > + crypto: crypto@30900000 { > + compatible = "fsl,sec-v4.0"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x30900000 0x40000>; > + ranges = <0 0x30900000 0x40000>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_AHB>, > + <&clk IMX8MQ_CLK_IPG_ROOT>; > + clock-names = "aclk", "ipg"; > + > + sec_jr0: jr@1000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x1000 0x1000>; > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr1: jr@2000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x2000 0x1000>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr2: jr@3000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x3000 0x1000>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > i2c1: i2c@30a20000 { > compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > reg = <0x30a20000 0x10000>; >
On Fri, Aug 30, 2019 at 10:05 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote: > > Add node for CAAM - Cryptographic Acceleration and Assurance Module. > > Signed-off-by: Horia Geantă <horia.geanta@nxp.com> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> The patch itself looks good to me. Acked-by: Li Yang <leoyang.li@nxp.com> > Cc: Cory Tusar <cory.tusar@zii.aero> > Cc: Chris Healy <cphealy@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Iuliana Prodan <iuliana.prodan@nxp.com> > Cc: linux-crypto@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > > Shawn: > > Just a bit of a context: as per this thread > https://lore.kernel.org/linux-crypto/20190830131547.GA27480@gondor.apana.org.au/ > I am hoping I can get and Ack from you for this patch, so it can go > via cryptodev tree. The dts is describing the hardware and normally update to it shouldn't break old drivers. Not sure if this time the dts change is depending on driver change again? I remember previously arm-soc maintainer prefer to have dts changes merged with soc trees as a common practice. Regards, Leo > > Thanks, > Andrey Smirnov > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index d09b808eff87..752d5a61878c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -728,6 +728,36 @@ > status = "disabled"; > }; > > + crypto: crypto@30900000 { > + compatible = "fsl,sec-v4.0"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x30900000 0x40000>; > + ranges = <0 0x30900000 0x40000>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_AHB>, > + <&clk IMX8MQ_CLK_IPG_ROOT>; > + clock-names = "aclk", "ipg"; > + > + sec_jr0: jr@1000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x1000 0x1000>; > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr1: jr@2000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x2000 0x1000>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr2: jr@3000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x3000 0x1000>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > i2c1: i2c@30a20000 { > compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > reg = <0x30a20000 0x10000>; > -- > 2.21.0 >
On Fri, Aug 30, 2019 at 02:01:39PM -0700, Andrey Smirnov wrote: > Add node for CAAM - Cryptographic Acceleration and Assurance Module. > > Signed-off-by: Horia Geantă <horia.geanta@nxp.com> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > Cc: Cory Tusar <cory.tusar@zii.aero> > Cc: Chris Healy <cphealy@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Iuliana Prodan <iuliana.prodan@nxp.com> > Cc: linux-crypto@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > > Shawn: > > Just a bit of a context: as per this thread > https://lore.kernel.org/linux-crypto/20190830131547.GA27480@gondor.apana.org.au/ > I am hoping I can get and Ack from you for this patch, so it can go > via cryptodev tree. > > Thanks, > Andrey Smirnov > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++ > 1 file changed, 30 insertions(+) Patch applied. Thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d09b808eff87..752d5a61878c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -728,6 +728,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_AHB>, + <&clk IMX8MQ_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a20000 0x10000>;